Abstract: A set of submission queues associated with a host system is identified. A first set of internal queues and a second set of internal queues is generated based on the set of submission queues. Responsive to fetching a first memory access command pending in a submission queue of the set of submission queues, a first internal queue of the first set of internal queues is populated. Responsive to processing the first memory access command from the first internal queue of the first set of internal queues, a second internal queue of the second set of internal queues is populated. Responsive to completion of the first memory access command from the second internal queue of the second set of internal queues, an indication of the completion of the first memory access command is returned to the host system.

Abstract: A system and method for a memory sub-system to reduce latency by prefetching data blocks and preloading them into host memory of a host system. An example system including a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request of a host system to access a data block in the memory device; determining the data block stored in a first buffer in host memory is related to a set of one or more data blocks stored at the memory device; and storing the set of one or more data blocks in a second buffer in the host memory, wherein the first buffer is controlled by the host system and the second buffer is controlled by a memory sub-system.

Abstract: A host submits a command to a memory device, where a host status indicator (ID) for the host and a memory device status ID for the memory device are assigned with the command in at least one of a status command slot related to the command. An interrupt signal asserted during processing of the command is determined, where the interrupt signal is indicative of a change in at least one of the host status ID and the memory device status ID. After determining that the interrupt signal is asserted at least one of the host status ID and the memory device status ID are read. Based on the read information, a failure in at least one of the host and device is corrected prior to initiation of a timeout process.

Abstract: A set of submission queues associated with a host system is identified. A first set of internal queues and a second set of internal queues is generated based on the set of submission queues. Responsive to fetching a first memory access command pending in a submission queue of the set of submission queues, a first internal queue of the first set of internal queues is populated. Responsive to processing the first memory access command from the first internal queue of the first set of internal queues, a second internal queue of the second set of internal queues is populated. Responsive to completion of the first memory access command from the second internal queue of the second set of internal queues, an indication of the completion of the first memory access command is returned to the host system.

Abstract: A system and method for a memory sub-system to reduce latency by prefetching data blocks and preloading them into host memory of a host system. An example system including a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request of a host system to access a data block in the memory device; transmitting a response to the host system that indicates the data block is stored in a first buffer in host memory; determining the data block is related to a set of one or more data blocks stored at the memory device; and storing the set of one or more data blocks in a second buffer in the host memory, wherein the first buffer is controlled by the host system and the second buffer is controlled by a memory sub-system.

Abstract: A set of submission queues associated with a host system is identified. A first set of internal queues and a second set of internal queues is generated based on the set of submission queues. Responsive to fetching a first memory access command pending in a submission queue of the set of submission queues, a first internal queue of the first set of internal queues is populated. Responsive to processing the first memory access command from the first internal queue of the first set of internal queues, a second internal queue of the second set of internal queues is populated. Responsive to completion of the first memory access command from the second internal queue of the second set of internal queues, an indication of the completion of the first memory access command is returned to the host system.

Abstract: A system and method for a memory sub-system to reduce latency by prefetching data blocks and preloading them into host memory of a host system. An example system including a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request of a host system to access a data block in the memory device; transmitting a response to the host system that indicates the data block is stored in a first buffer in host memory; determining the data block is related to a set of one or more data blocks stored at the memory device; and storing the set of one or more data blocks in a second buffer in the host memory, wherein the first buffer is controlled by the host system and the second buffer is controlled by a memory sub-system.

Abstract: A system for validating a power cycle for an emulated Peripheral Component Interconnect express (PCIe) storage device, the system including: an emulating and virtualizing unit hosting a virtual machine; a PCIe bridge device; and emulated PCIe storage devices, wherein the PCIe bridge device: receives a bridge register value that indicates a “Power ON” or “Power OFF” condition; receives a request from the virtual machine to perform actions corresponding to the bridge register value; detects a condition associated with the bridge register value; performs the actions corresponding to the detected condition on the emulated PCIe storage devices to emulate the “Power ON” or “Power OFF” condition for the emulated PCIe storage devices; and validates a power cycle of the emulated PCIe storage devices based on a pre-stored vendor value and a corresponding pre-stored condition for the emulated “Power ON” or “Power OFF” condition for the emulated PCIe storage devices.

Abstract: The present disclosure describes a method and a system for sending data packets to improve Quality of Service in Non-Volatile Memory express (NVMe) aware Remote Direct Memory Access (RDMA) network, including receiving, by a host RNIC, RDMA command from a host initiator, wherein the RDMA command comprises data packets, arranging, by the host RNIC, the data packets based on weights and priorities of RDMA queue pairs, storing, by the host RNIC, the data packets in a host queue from host RDMA queue pairs based on the weights and priorities of the RDMA queue pairs, and sending, by the host RNIC, the data packets through host virtual lanes to a target RNIC.

Abstract: The present disclosure describes a method and a system for sending data packets to improve Quality of Service in Non-Volatile Memory express (NVMe) aware Remote Direct Memory Access (RDMA) network, including receiving, by a host RNIC, RDMA command from a host initiator, wherein the RDMA command comprises data packets, arranging, by the host RNIC, the data packets based on weights and priorities of RDMA queue pairs, storing, by the host RNIC, the data packets in a host queue from host RDMA queue pairs based on the weights and priorities of the RDMA queue pairs, and sending, by the host RNIC, the data packets through host virtual lanes to a target RNIC.

Abstract: A first host system in a multipath storage system acts on behalf of a second host system when the second host system is unable to access a solid state drive (SSD). The first host system configures a bitmap table using an SSD controller of the first host system to access memory of the SSD associated with the second host system. The memory accessed on behalf of the second host system may be in a region including persistent memory, base address register memory and/or controller memory buffer of the second host system.

Abstract: Systems and methods for managing transfer of NVMeoF commands/responses between a host and a target are described. The systems and methods may initiate and convert at least one Input/Output request into at least one Non-Volatile Memory Express over Fabric (NVMeoF) command to access a storage device attached with the target device. A host may transmit the at least one NVMeoF command in a burst mode using a Remote Direct Memory Access (RDMA) Write packet to a pre-registered memory region of the target device. In response to reception of the at least one NVMeoF command, the target device may post at least one NVMeoF completion response corresponding to the at least one NVMeoF command using the RDMA Write packet to a pre-registered memory region of the host.

Abstract: Systems and methods for managing transfer of NVMeoF commands/responses between a host and a target are described. The systems and methods may initiate and convert at least one Input/Output request into at least one Non-Volatile Memory Express over Fabric (NVMeoF) command to access a storage device attached with the target device. A host may transmit the at least one NVMeoF command in a burst mode using a Remote Direct Memory Access (RDMA) Write packet to a pre-registered memory region of the target device. In response to reception of the at least one NVMeoF command, the target device may post at least one NVMeoF completion response corresponding to the at least one NVMeoF command using the RDMA Write packet to a pre-registered memory region of the host.