Abstract: A semiconductor device package and a method of making the same are provided. The semiconductor device includes a package substrate, a layer of conductive material, a group of channels, and a chip. The package substrate has a top layer. The top layer has a group of conductive vias formed therethrough. The conductive material layer is formed on the top layer of the package substrate. The group of channels are formed in the conductive material layer about at least some of the vias to define a group of contact pads on the vias. The chip is electrically coupled to the package substrate through the contact pads.

Abstract: A method of forming an underfilled chip package is provided. No-flow underfill material is deposited over a surface of a package substrate to form an underfill region. A die having a plurality of solder bumps is placed at an angle relative to the package substrate such that solder bumps adjacent a first side of the die contact the surface of the package substrate within the underfill region while solder bumps adjacent a second side of the die are generally located at a distance away from the surface of the package substrate. The second side of the die is moved toward the surface of the package substrate until the solder bumps adjacent the second side of the die contact the surface such that the underfill material is forced into the area between the plurality of bumps.

Abstract: A method of forming an underfilled chip package is provided. No-flow underfill material is deposited over a surface of a package substrate to form an underfill region. A die having a plurality of solder bumps is placed at an angle relative to the package substrate such that solder bumps adjacent a first side of the die contact the surface of the package substrate within the underfill region while solder bumps adjacent a second side of the die are generally located at a distance away from the surface of the package substrate. The second side of the die is moved toward the surface of the package substrate until the solder bumps adjacent the second side of the die contact the surface such that the underfill material is forced into the area between the plurality of bumps.

Abstract: In accordance with the present invention, a built-up bump pad structure and method for the same are provided. The bump pad structure includes a substrate, a bump pad disposed upon the substrate, a solder mask disposed upon the substrate defining an opening around the bump pad, and a conductive material deposited upon the bump pad such that the conductive material at least partially fills the opening around the bump pad.

Abstract: In one embodiment, an integrated circuit package includes a die associated with an integrated circuit and a die pad. The die has a bottom surface, and the pad has a top surface opposite the bottom surface of the die. Two or more bump pad traces are each coupled to the top surface of the pad, and one or more other traces are each coupled to the top surface of the pad in a corresponding inter-bump pad region between adjacent bump pad traces. A number of solder bumps each couple the die to the pad at a corresponding bump pad trace to provide electrical connectivity between circuitry associated with the die and circuitry associated with the die pad. Each inter-bump pad region is free from any solder mask material deposited to control collapse of the die towards the pad during a reflow process for bonding the die to the pad using the bumps, a supporting structure that contacts the die during the reflow process having been used instead.

Abstract: In accordance with the present invention, a built-up bump pad structure and method for the same are provided. The bump pad structure includes a substrate, a bump pad disposed upon the substrate, a solder mask disposed upon the substrate defining an opening around the bump pad, and a conductive material deposited upon the bump pad such that the conductive material at least partially fills the opening around the bump pad.

Abstract: In one embodiment, an integrated circuit package includes a die associated with an integrated circuit and a die pad. The die has a bottom surface, and the pad has a top surface opposite the bottom surface of the die. Two or more bump pad traces are each coupled to the top surface of the pad, and one or more other traces are each coupled to the top surface of the pad in a corresponding inter-bump pad region between adjacent bump pad traces. A number of solder bumps each couple the die to the pad at a corresponding bump pad trace to provide electrical connectivity between circuitry associated with the die and circuitry associated with the die pad. Each inter-bump pad region is free from any solder mask material deposited to control collapse of the die towards the pad during a reflow process for bonding the die to the pad using the bumps, a supporting structure that contacts the die during the reflow process having been used instead.

Abstract: A semiconductor device package and a method of making the same are provided. The semiconductor device includes a package substrate, a layer of conductive material, a group of channels, and a chip. The package substrate has a top layer. The top layer has a group of conductive vias formed therethrough. The conductive material layer is formed on the top layer of the package substrate. The group of channels are formed in the conductive material layer about at least some of the vias to define a group of contact pads on the vias. The chip is electrically coupled to the package substrate through the contact pads.

Abstract: A semiconductor device package and a method of making the same are provided. The semiconductor device includes a package substrate, a layer of conductive material, a group of channels, and a chip. The package substrate has a top layer. The top layer has a group of conductive vias formed therethrough. The conductive material layer is formed on the top layer of the package substrate. The group of channels are formed in the conductive material layer about at least some of the vias to define a group of contact pads on the vias. The chip is electrically coupled to the package substrate through the contact pads.

Abstract: A semiconductor device package and a method of making the same are provided. The semiconductor device includes a package substrate, a layer of conductive material, a group of channels, and a chip. The package substrate has a top layer. The top layer has a group of conductive vias formed therethrough. The conductive material layer is formed on the top layer of the package substrate. The group of channels are formed in the conductive material layer about at least some of the vias to define a group of contact pads on the vias. The chip is electrically coupled to the package substrate through the contact pads.