Patents by Inventor Muthu K. Kumar

Muthu K. Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10078363
    Abstract: An apparatus is provided that includes a microcontroller to facilitate data communication within a system comprising a plurality of peripheral devices, a power manager to put the microcontroller into a sleep state to save power, and an I/O controller to enable communication between two or more particular peripheral devices in the plurality of peripheral devices without involvement of the microcontroller while the microcontroller is in the sleep state. The microcontroller is to wake from the sleep state in response to at least one signal from a component of the system external to the microcontroller and communication between at least some of the plurality of peripheral devices is facilitated using the microcontroller when in an awake state.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: September 18, 2018
    Assignee: Intel Corporation
    Inventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner D. Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Fleming, Uma M. Gadamsetty
  • Publication number: 20160132101
    Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.
    Type: Application
    Filed: January 15, 2016
    Publication date: May 12, 2016
    Inventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner D. Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Fleming, Uma M. Gadamsetty
  • Patent number: 9305562
    Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: April 5, 2016
    Assignee: Intel Corporation
    Inventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner D. Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Fleming, Uma M. Gadamsetty
  • Publication number: 20150228290
    Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.
    Type: Application
    Filed: April 20, 2015
    Publication date: August 13, 2015
    Inventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner D. Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Fleming, Uma M. Gadamsetty
  • Patent number: 9015511
    Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: April 21, 2015
    Assignee: Intel Corporation
    Inventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner D. Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Fleming, Uma M. Gadamsetty
  • Publication number: 20130346664
    Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.
    Type: Application
    Filed: August 27, 2013
    Publication date: December 26, 2013
    Inventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Flemming, Uma M. Gadamsetty
  • Patent number: 8522063
    Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: August 27, 2013
    Assignee: Intel Corporation
    Inventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Flemming, Uma M. Gadamsetty
  • Publication number: 20120210036
    Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.
    Type: Application
    Filed: April 24, 2012
    Publication date: August 16, 2012
    Inventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Flemming, Uma M. Gadamsetty
  • Patent number: 8166325
    Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: April 24, 2012
    Assignee: Intel Corporation
    Inventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Flemming, Uma M. Gadamsetty
  • Publication number: 20090019185
    Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.
    Type: Application
    Filed: September 22, 2008
    Publication date: January 15, 2009
    Inventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Flemming, Uma M. Gadamsetty
  • Patent number: 7428650
    Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: September 23, 2008
    Assignee: Intel Corporation
    Inventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Flemming, Uma M. Gadamsetty
  • Patent number: 7421597
    Abstract: A method is described that involves operating a computing system within a normal on state and transitioning from the normal on state to a main CPU/OS based state. In the main CPU/OS based state one or more components of the computing system are inactivated so as to cause the computing system to consume less power in the main CPU/OS based state than in the normal on state. The computing system is able to execute software application routines on a main CPU and a main OS of the computing system while in the main CPU/OS based state.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: September 2, 2008
    Assignee: Intel Corporation
    Inventors: James P. Kardach, Jeffrey L. Huckins, Kristoffer D. Fleming, Uma M. Gadamsetty, Vivek Gupta, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand
  • Patent number: 7406610
    Abstract: A method is described that involves operating a computing system within a normal on state and transitioning from the normal on state to a main CPU/OS based state. In the main CPU/OS based state one or more components of the computing system are inactivated so as to cause the computing system to consume less power in the main CPU/OS based state than in the normal on state. The computing system is able to execute software application routines on a main CPU and a main OS of the computing system while in the main CPU/OS based state.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: July 29, 2008
    Assignee: Intel Corporation
    Inventors: James P. Kardach, Jeffrey L. Huckins, Kristoffer D. Fleming, Uma M. Gadamsetty, Vivek Gupta, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand
  • Patent number: 7263331
    Abstract: A method and apparatus for a user to interface with a mobile computing device is disclosed. In one embodiment, a method comprises sharing a Bluetooth communications module between a primary processor system and a secondary processor system.
    Type: Grant
    Filed: September 15, 2003
    Date of Patent: August 28, 2007
    Assignee: Intel Corporation
    Inventors: Vivek G. Gupta, James Kardach, Brian V. Belmont, Muthu K. Kumar
  • Patent number: 7114090
    Abstract: A method is described that involves operating a computing system within a normal on state and transitioning from the normal on state to a main CPU/OS based state. In the main CPU/OS based state one or more components of the computing system are inactivated so as to cause the computing system to consume less power in the main CPU/OS based state than in the normal on state. The computing system is able to execute software application routines on a main CPU and a main OS of the computing system while in the main CPU/OS based state.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: September 26, 2006
    Assignee: Intel Corporation
    Inventors: James P. Kardach, Jeffrey L. Huckins, Kristoffer D. Fleming, Uma M. Gadamsetty, Vivek Gupta, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand
  • Patent number: 7080271
    Abstract: A computing system is described that includes an I/O unit interface that is deactivated while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit that is coupled to both the I/O unit interface and the controller.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: July 18, 2006
    Assignee: Intel Corporation
    Inventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Flemming, Uma M. Gadamsetty
  • Publication number: 20040163005
    Abstract: A method is described that involves operating a computing system within a normal on state and transitioning from the normal on state to a main CPU/OS based state. In the main CPU/OS based state one or more components of the computing system are inactivated so as to cause the computing system to consume less power in the main CPU/OS based state than in the normal on state. The computing system is able to execute software application routines on a main CPU and a main OS of the computing system while in the main CPU/OS based state.
    Type: Application
    Filed: February 14, 2003
    Publication date: August 19, 2004
    Inventors: James P. Kardach, Jeffrey L. Huckins, Kristoffer D. Fleming, Uma M. Gadamsetty, Vivek Gupta, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand
  • Publication number: 20040162922
    Abstract: A computing system is described that includes an I/O unit interface that is deactivated while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an 110 unit that is coupled to both the I/O unit interface and the controller.
    Type: Application
    Filed: February 14, 2003
    Publication date: August 19, 2004
    Inventors: James P. Kardach, Brian V. Belmont, Muthu K. Kumar, Riley W. Jackson, Gunner Danneels, Richard A. Forand, Vivek Gupta, Jeffrey L. Huckins, Kristoffer D. Flemming, Uma M. Gadamsetty