Abstract: A compound semiconductor device including a MISFET and a thyristor connected in series wherein either the withstanding voltage between the MISFET p base layer and the thyristor p base layer is set lower than the withstanding voltage of the MISFET, the MISFET is turned off under a condition that the MISFET p base layer and the thyristor p base layer are connected via a p channel or the lateral resistance of the thyristor p base layer is reduced, thereby the safe operating region of the compound semiconductor device is extended.

Abstract: An inverter device includes plural modules, each module being formed by a series circuit having a parallel circuit of a first switching device and a first diode, and a parallel circuit of a second switching device and a second diode, allowing a reduced size, high reliability, high frequency switching and low noise. Each module forms one arm portion of the inverter. Lifetimes of the diodes and the switching devices are set in a manner to equalize losses in the inverter. Preferably, insulated gate bipolar transistors (IGBTs) formed by diffusion are used as the switching devices since the lifetimes of these devices can easily be adjusted to optimize design of the inverter.

Abstract: The present invention provides a semiconductor device comprising, at least a pair of an insulated gate bipolar transistor, and a diode, both of which are in a reverse parallel connection with each other, wherein the resistivity of the base layer of the lowest impurity concentration in the diode is lower than that of the base layer of the lowest impurity concentration in the insulated gate bipolar transistor, and wherein a breakdown voltage of said insulated gate bipolar transistor at the time of switching from conduction state to blocking state is lower than a breakdown voltage of said insulated gate bipolar transistor and said diode at the time of blocking state.

Abstract: A high voltage semiconductor device is provided with a p layer which forms a main pn- junction, a plurality of p layers which surround the p layer in a ring form, a ring-like n+ layer which further surrounds those p layers, forward field plates extending in the peripheral direction and reverse field plates extending in the inside direction, the field plates being in contact at a low resistance with the p and n+ layers and reaching the surface of an n- layer through an insulating film, the area of the field plates being not less than one half of the n- surface. This arrangement is effective in stabilizing the blocking voltage of a high voltage semiconductor device which is used in a severe environment, and is vey effective in improving the reliabilty of a high voltage control unit.

Abstract: The present invention is directed to a semiconductor device which can achieve high current density and which has a high reliability. In the insulated gate semiconductor device according to the present invention, a plurality of insulating gates are provided, with each two adjacent insulating gates being spaced from each other, the insulating gates being provided on a second semiconductor region of a first conductivity type. A first semiconductor region, of the same or different conductivity type from that of the second semiconductor region, extends from a surface of the second semiconductor region opposed to the surface thereof having the insulating gates thereon. A plurality of third semiconductor regions are provided in the second semiconductor region, between the insulating gates and aligned therewith, and two fourth semiconductor regions are provided extending into each of the third semiconductor regions, aligned with the sides of adjacent insulating gates.

Abstract: A first power semiconductor device with a semiconductor base to which an emitter wire electrode is connected through an emitter bonding pad and a gate wire electrode is connected through a gate bonding pad, wherein the gate bonding pad comprises a silicon oxide film, a silicon crystal layer and a gate wiring electrode made of aluminum containing silicon which are successively formed on the semiconductor base, and the gate wire electrode is connected to the gate wiring electrode. A second power semiconductor device wherein the emitter bonding pad is an emitter wiring electrode made of aluminum containing silicon which is directly formed on the semiconductor base, and the emitter wire electrode is bonded to the emitter wiring electrode.

Abstract: A compound semiconductor device is provided which includes a thyristor region constructed by four continuous layers of p-n-p-n and an MOSFET region which is formed in the intermediate n layer of the thyristor region so as to be away from the intermediate p layer. The MOSFET is constructed by a p well layer, a source layer, and a drain layer. One main electrode of the device is in ohmic contact with the outside p layer of the thyristor region while the other main electrode is in ohmic contact with the source layer and well layer of the MOSFET region. An arrangement is provided for electrically connecting the outside n layer of the thyristor region and the drain layer of the MOSFET region. Also, a first insulating gate is formed on the well layer between the source layer and the drain layer of the MOSFET region and a second insulating gate is formed on the intermediate p layer of the thyristor region with the first and second insulating gates being electrically connected.

Abstract: An inverter device includes plural modules, each module being formed by a series circuit having a parallel circuit of a first switching device and a first diode, and a parallel circuit of a second switching device and a second diode, allowing a reduced size, high reliability, high frequency switching and low noise. Each module forms one arm portion of the inverter. Lifetimes of the diodes and the switching devices are set in a manner to equalize losses in the inverter. Preferably, insulated gate bipolar transistors (IGBTs) formed by diffusion are used as the switching devices since the lifetimes of these devices can easily be adjusted to optimize design of the inverter.

Abstract: A semiconductor integrated circuit unit, suitable for the control of a motor, has an integrated structure within the same semiconductor substrate, comprising an inverter circuit, drive circuits for driving the switching elements of the inverter circuit, an internal power source circuit for supplying power to the drive circuits which drive the upper arm side of the inverter circuit, and a logical circuit for transmitting a signal to the drive circuits which drive the upper arm side of the inverter circuit.

Abstract: A compound semiconductor device is provided which includes a thyristor region constructed by four continuous layers of p-n-p-n and an MOSFET region which is formed in the intermediate n layer of the thyristor region so as to be away from the intermediate p layer. The MOSFET is constructed by a p well layer, a source layer, and a drain layer. One main electrode of the device is in ohmic contact with the outside p layer of the thyristor region. While the other main electrode is in ohmic contact with the source layer and well layer of the MOSFET region. An arrangement is provided for electrically connecting the outside n layer of the thyristor region and the drain layer of the MOSFET region. Also, a first insulating gate is formed on the well layer between the source layer and the drain layer of the MOSFET region and a second insulating gate is formed on the intermediate p layer of the thyristor region; with the first and second insulating gates being electrically connected.

Abstract: A lateral insulated-gate bipolar transistor has a drift region having therein a base layer and a collector layer. An emitter layer is formed in the base layer. A gate electrode structure, comprising a control electrode and gate insulating layer, contacts the base layer, and also contacts the drift layer and the emitter layer. An emitter electrode contacts the emitter layer, and also the base layer, and a collector electrode contacts the collector layer. The emitter and collector electrodes are elongate and the ratio of their resistances per unit length is in the range of 0.5 to 2.0. This reduces the possibility of a localized high current density along the electrodes, thereby reducing the risk of latch-up due to parasitic thyristors. The collector and emitter electrodes may be of the same width and thickness, or of different widths and thicknesses, or may each have an auxiliary part (for example, in a multi-layer wiring arrangement), so that their resistances per unit length are in the desired range.

Abstract: The present invention relates to a semiconductor device having an n-type semiconductor region forming one of the main surfaces of a semiconductor substrate, with a plurality of p-type semiconductor regions formed in the n-type semiconductor region. Two exposed n-type semiconductor regions are formed on each of the p-type semiconductor regions, with a main electrode formed on the n-type semiconductor regions and the exposed p-type semiconductor region therebetween. An insulated gate extends from one of the n-type semiconductor regions in one of the p-type semiconductor regions to a closer one of the n-type semiconductor regions in an adjacent p-type semiconductor region. The length of the insulated gate is longer than a distance between adjacent insulated gates.

Abstract: A semiconductor device includes a diode having a Schottky barrier and a MOS transistor integrally formed in one and the same semiconductor substrate in which the diode and MOS transistor have their main electrode in common use. The diode has a first diode portion having a pn junction in a current-passing direction and a second diode portion having a combination of the Schottky barrier and another pn junction in the current passing direction.

Abstract: In a module using a high-speed switching element such as an IGBT for a high-speed inverter, a matching condition is established between the switching characteristic of the IGBT and the recovery characteristic of the diode to be connected thereto in an anti-parallel fashion. As a result, the oscillating voltage appearing in the inverter circuit is suppressed to prevent erroneous operation of the inverter system.

Abstract: A semiconductor device comprises a semiconductor substrate, a semiconductor layer of a first conductivity type formed on said semiconductor substrate, a first semiconductor well region of a second conductivity type and second semiconductor well regions of the second conductivity type, the latter two types of regions being formed in said semiconductor layer. The first semiconductor well region is located at the peripheral area of the semiconductor, and the well is deeper than the well of the second semiconductor well regions. Third semiconductor well regions of the first conductivity type are formed in the second semiconductor well regions. Gate electrodes and an emitter (source) electrode are formed at specified positions on the upper surface of the semiconductor device, and a collector (drain) electrode is formed on the bottom surface.

Abstract: A semiconductor integrated circuit unit, suitable for the control of a motor, has an integrated structure within the same semiconductor substrate, comprising an inverter circuit, drive circuits for driving the switching elements of the inverter circuit, an internal power source circuit for supplying power to the drive circuits which drive the upper arm side of the inverter circuit, and a logical circuit for transmitting a signal to the drive circuits which drive the upper arm side of the inverter circuit.

Abstract: A semiconductor device comprises a semiconductor substrate, a semiconductor layer of a first conductivity type formed on said semiconductor substrate, a first semiconductor well region of a second conductivity type and second semiconductor well regions of the second conductivity type, the latter two types of regions being formed in said semiconductor layer. The first semiconductor well region is located at the peripheral area of the semiconductor, and the well is deeper than the well of the second semiconductor well regions. Third semiconductor well regions of the first conductivity type are formed in the second semiconductor well regions. Gate electrodes and an emitter (source) electrode are formed at specified positions on the upper surface of the semiconductor device, and a collector (drain) electrode is formed on the bottom surface.

Abstract: A method for fabricating an insulated gate semiconductor device comprises the steps of forming insulated gates on an n.sup.- -layer surface, forming p-well layers in the n.sup.- -layer using the insulated gates as masks, forming phosphosilicate glass layers on the side walls of the insulated gates and diffusing the impurities from the phosphosilicate glass layers into the p-well layers to form n.sup.30 -source layer.

Abstract: A semiconductor device is provided wherein a first diode having a pn junction and a second diode having a combination of a Schottky barrier and a pn junction in a current-passing direction are provided side by side in a direction perpendicular to the current-passing direction. When a forward current with a current density J.sub.F is passed into the second diode, the relation ##EQU1## is established in a forward voltage V.sub.F range of 0.1 (V) to 0.3 (V), where k represents the Boltzmann constant (.apprxeq.1.38.times.10.sup.-23 J/K), T represents the absolute temperature, and q represents the quantity of electron charges (.apprxeq.1.6.times.10.sup.-19 C).

Abstract: A lateral insulated gate bipolar transistor comprises a p layer and a p.sup.+ layer provided apart from each other and extending from a surface of an n.sup.- layer into the n.sup.- layer, an n.sup.+ layer provided extending from a surface of the p layer into the p layer, a first main electrode provided in ohmic contact with the n.sup.+ layer and the p layer, a second main electrode provided in ohmic contact with the p.sup.+ layer, and a control electrode provided through an insulating film on the n.sup.+ layer, the p layer and the n.sup.- layer on the side of the first main electrode away from the second main electrode.