Abstract: In a semiconductor device, a plurality of interface cells is disposed on four sides of an LSI chip in connection with a logic circuit area including a plurality of logic cells. Each interface cell may include four functional blocks which are vertically or horizontally aligned without being rotated, thus forming an I/O buffer. The left I/O buffer has a vertical layout in which functional blocks are vertically aligned, whilst the upper I/O buffer has a horizontal layout in which functional blocks are horizontally aligned. This makes it possible to fix the same length direction of gates of transistors with respect to both the functional blocks of I/O buffers and the logic cells, so that engineers do not need to consider characteristic variations of transistors due to positional differences of transistors when designing the circuitry of an LSI chip.

Abstract: Provided is a power supply noise resistance testing circuit, in which a test pattern is applied to a data input portion of a functional block formed on a semiconductor chip and a voltage on which a power supply noise is superimposed is supplied to a power supply portion of the functional block, thereby testing a power supply noise resistance of the functional block. In the power supply noise resistance testing circuit, a power supply noise generating circuit for generating the power supply noise is provided around or inside the functional block. A power supply of the power supply noise generating circuit is connected with a power supply of the functional block through a connection path to transmit the power supply noise.

Abstract: An apparatus, includes a counter which counts a frequency of input of a first signal, a delay controller which generates a second signal by adding a delay to the first signal, the delay corresponding to the frequency, and a control circuit which halts the counter counting the frequency, when a phase difference between the first signal and the second signal is a predetermined value.

Abstract: An apparatus, includes a counter which counts a frequency of input of a first signal, a delay controller which generates a second signal by adding a delay to the first signal, the delay corresponding to the frequency, and a control circuit which halts the counter counting the frequency, when a phase difference between the first signal and the second signal is a predetermined value.

Abstract: The memory interface control circuit includes a mask-release-signal generation circuit which generates a basic mask-release signal from a data strobe signal input from a DRAM and a read timing signal indicative of a read start, a mask-release-signal generation circuit which generates a mask signal from a basic mask-release signal and a read mode signal indicative of a read mode of the DRAM, and a strobe signal generation circuit which generates an internal data strobe signal from a delayed data strobe signal and the mask signal.

Abstract: Provided is a power supply noise resistance testing circuit, in which a test pattern is applied to a data input portion of a functional block formed on a semiconductor chip and a voltage on which a power supply noise is superimposed is supplied to a power supply portion of the functional block, thereby testing a power supply noise resistance of the functional block. In the power supply noise resistance testing circuit, a power supply noise generating circuit for generating the power supply noise is provided around or inside the functional block. A power supply of the power supply noise generating circuit is connected with a power supply of the functional block through a connection path to transmit the power supply noise.

Abstract: The memory interface control circuit includes a mask-release-signal generation circuit which generates a basic mask-release signal from a data strobe signal input from a DRAM and a read timing signal indicative of a read start, a mask-release-signal generation circuit which generates a mask signal from a basic mask-release signal and a read mode signal indicative of a read mode of the DRAM, and a strobe signal generation circuit which generates an internal data strobe signal from a delayed data strobe signal and the mask signal.

Abstract: According to one embodiment, one variable delay circuit adjusts a data strobe signal to be delayed, a control circuit generates an auxiliary signal, another variable delay circuit adjusts the auxiliary signal to be delayed, a mask generation circuit generates a mask signal based on the delayed data strobe signal and the delayed auxiliary signal, and an AND circuit applies the mask signal to the delayed data strobe signal, thereby generating a data strobe signal without a glitch. A write address signal generation circuit generates a control signal for controlling a flip-flop group based on the data strobe signal without the glitch, and the flip-flop group stores read data according to the control signal. A selector selects data from among pieces of data stored in the flip-flop group according to the read address signal.

Abstract: According to one embodiment, one variable delay circuit adjusts a data strobe signal to be delayed, a control circuit generates an auxiliary signal, another variable delay circuit adjusts the auxiliary signal to be delayed, a mask generation circuit generates a mask signal based on the delayed data strobe signal and the delayed auxiliary signal, and an AND circuit applies the mask signal to the delayed data strobe signal, thereby generating a data strobe signal without a glitch. A write address signal generation circuit generates a control signal for controlling a flip-flop group based on the data strobe signal without the glitch, and the flip-flop group stores read data according to the control signal. A selector selects data from among pieces of data stored in the flip-flop group according to the read address signal.