Abstract: An oscillation circuit includes a first current source having dependency of current value/temperature exhibiting a first characteristic; a second current source having dependency of current value/temperature exhibiting a second characteristic; a first conversion section, input with a current from the first current source, that outputs a first current having a specific characteristic which is converted from the first characteristic; a second conversion section, input with a current from the second current source, that outputs a second current having a specific characteristic which is converted from the second characteristic; a subtraction section, input with the first and the second current, that outputs a difference current that is a difference between the first and the second current; and a clock generation section that generates a clock signal by alternately charging and discharging a first capacitor and a second capacitor based on the difference current.

Abstract: The present invention provides an oscillation circuit including: a first current source having dependency of current value/temperature exhibiting a first characteristic; a second current source having dependency of current value/temperature exhibiting a second characteristic; a first conversion section, input with a current from the first current source, that outputs a first current having a specific characteristic which is converted from the first characteristic; a second conversion section, input with a current from the second current source, that outputs a second current having a specific characteristic which is converted from the second characteristic; a subtraction section, input with the first and the second current, that outputs a difference current that is a difference between the first and the second current; and a clock generation section that generates a clock signal by alternately charging and discharging a first and a second capacitor based on the difference current.

Abstract: A control circuit of a DC/DC converter stabilizing driving a current while supplying a driving voltage to a load comprises a current detection circuit for comparing a current detection signal indicative of a current flowing through a switching transistor of the DC/DC converter with a predetermined threshold to generate an OFF signal, a timer circuit for generating an ON signal that is asserted after a predetermined time period has elapsed since an assertion of the OFF signal, a pulse generation circuit for generating a pulse signal, and a driver for driving the switching transistor based on the pulse signal, where the timer circuit includes a first capacitor, a current source for generating a charging current, an arithmetic circuit for generating a threshold voltage, and an first comparator configured to compare a voltage of the first capacitor and the threshold voltage.

Abstract: A control circuit of a DC/DC converter stabilizing driving a current while supplying a driving voltage to a load comprises a current detection circuit for comparing a current detection signal indicative of a current flowing through a switching transistor of the DC/DC converter with a predetermined threshold to generate an OFF signal, a timer circuit for generating an ON signal that is asserted after a predetermined time period has elapsed since an assertion of the OFF signal, a pulse generation circuit for generating a pulse signal, and a driver for driving the switching transistor based on the pulse signal, where the timer circuit includes a first capacitor, a current source for generating a charging current, an arithmetic circuit for generating a threshold voltage, and an first comparator configured to compare a voltage of the first capacitor and the threshold voltage.

Abstract: A semiconductor integrated circuit includes a first controlling circuit section, a level transforming circuit, a first buffer circuit, a second buffer circuit, and an overvoltage protecting circuit. A first n-channel type MOS transistor is provided in the first buffer circuit and a second p-channel type MOS transistor is provided in the second buffer circuit. Thus, faster operation can be obtained, and voltage between the source and drain of a third p-channel type MOS transistor and a third n-channel type MOS transistor of the overvoltage protecting circuit, impressed when output signal OUT changes, can be decreased.

Abstract: A differential input circuit comprising only low withstand voltage transistors, which reliability is not affected even if a high power supply voltage is used. The first and second clamp circuits input the differential input signals IN+ and IN? which vibrate between the ground potential and the power supply potential VDD, and output the signals INH+ and INH? of which the lower limit potential is the bias potential BIAS2, and the signals INL+ and INL? of which the upper limit potential is the bias potential BIAS3. Using these signals, the folded cascode amplification circuit generates the differential output signals OUT+ and OUT? which vibrate between the ground potential and the power supply potential VCC (VCC<VDD). The bias circuit generates the bias potential of the transistor inside the folded cascode amplification circuit.

Abstract: A level trasnforming circuit includes a first CMOS circuit, a first intermediate circuit, a second intermediate circuit, a second CMOS circuit, a seventh p-channel type MOS transistor, and an eighth p-channel type MOS transistor; wherein the first intermediate circuit and the second intermediate circuit form a latch circuit. To this latch circuit, writing of data is performed by way of the seventh p-channel type MOS transistor and the eighth p-channel type MOS transistor. Thus, the latch circuit is made up of a CMOS inverter. Therefore, fast operation can be obtained and drop of drivability can be restrained.

Abstract: A bidirectional bus driver includes a first buffer which supplies the data signal to the second bus when the first control signal is enabled; a second buffer which supplies the data signal to the first bus when the first control signal is enabled; a first control; a second control; a third buffer which supplies a signal in the second bus to the first bus when the second control signal is enabled; and a fourth buffer which supplies a signal in the first bus to the second bus when the third control signal is enabled. The first control circuit enables the second control signal when a signal transition is detected in the second bus while the first control signal is not enabled; and the second control circuit enables the third control signal when a signal transition is detected in the first bus while the first control signal is not enabled.

Abstract: What is disclosed is: a semiconductor integrated circuit comprising; a first controlling circuit section, a level transforming circuit, a first buffer circuit, a second buffer circuit, an overvoltage protecting circuit; wherein a first n-channel type MOS transistor is provided in the first buffer circuit and a second p-channel type MOS transistor is provided in the second buffer circuit. Thus, faster operation can be obtained. And, voltage between source and drain of a third p-channel type MOS transistor and a third n-channel type MOS transistor of the overvoltage protecting circuit, impressed when output signal OUT changes, can be decreased.

Abstract: A bidirectional bus driver includes a first buffer which supplies the data signal to the second bus when the first control signal is enabled; a second buffer which supplies the data signal to the first bus when the first control signal is enabled; a first control; a second control; a third buffer which supplies a signal in the second bus to the first bus when the second control signal is enabled; and a fourth buffer which supplies a signal in the first bus to the second bus when the third control signal is enabled. The first control circuit enables the second control signal when a signal transition is detected in the second bus while the first control signal is not enabled; and the second control circuit enables the third control signal when a signal transition is detected in the first bus while the first control signal is not enabled.

Abstract: A differential input circuit comprising only low withstand voltage transistors, which reliability is not affected even if a high power supply voltage is used. The first and second clamp circuits input the differential input signals IN+ and IN− which vibrate between the ground potential and the power supply potential VDD, and output the signals INH+ and INH− of which the lower limit potential is the bias potential BIAS2, and the signals INL+ and INL− of which the upper limit potential is the bias potential BIAS3. Using these signals, the folded cascode amplification circuit generates the differential output signals OUT+ and OUT− which vibrate between the ground potential and the power supply potential VCC (VCC<VDD). The bias circuit generates the bias potential of the transistor inside the folded cascode amplification circuit.

Abstract: What is disclosed is: a level transforming circuit comprising; a first CMOS circuit (10), a first intermediate circuit (30), a second intermediate circuit (40), a second CMOS circuit (20), a seventh p-channel type MOS transistor (51p), and an eighth p-channel type MOS transistor (52p); wherein the first intermediate circuit (30) and the second intermediate circuit (40) comprise a latch circuit. And, to this latch circuit, writing of data is performed by way of the seventh p-channel type MOS transistor (51p) and the eighth p-channel type MOS transistor (52p). Thus, a latch circuit is made up of CMOS inverter. Therefore, fast operation can be obtained and drop of drivability can be restrained.

Abstract: A D/A converter is provided with an equal current cell matrix achieved by arraying in a matrix equal current cells each having a current switch portion, a row decoder that makes selections in the direction of the rows in the equal current cell matrix and a column decoder that makes selections in the direction of the columns in the equal current cell matrix. The D/A converter is characterized in that the equal current cells are each provided with a latch circuit for achieving synchronization of an output signal from the row decoder and an output signal from the column decoder that are input to the current switch portion. Since the current is switched by the latch circuit, glitches can be completely eliminated from the signals input to the current switch portion by taking into consideration the lengths of delays at the row decoder and the column decoder and the timing of the clock to achieve an improvement in the S/N ratio. Furthermore, since no NMOS capacitance is required, the power consumption is reduced.