Patents by Inventor Mutsuyoshi Ito

Mutsuyoshi Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070126030
    Abstract: Disclosed herein is a semiconductor device including: a semiconductor chip; a first insulating layer covering the semiconductor chip in a condition where at least a portion of a terminal electrode of the semiconductor chip is exposed; a second insulating layer formed over the first insulating layer; and a rewiring layer extracting the terminal electrode of the semiconductor chip via the second insulating layer to a position of connection with an external circuit; wherein an underlying layer for plating connected with the terminal electrode is provided in an existing area of the terminal electrode alone or in a region covering from the existing area to above the first insulating layer, and at least a part of the rewiring layer is formed of a plated layer formed on the underlying layer.
    Type: Application
    Filed: November 18, 2006
    Publication date: June 7, 2007
    Inventor: Mutsuyoshi Ito
  • Patent number: 7002236
    Abstract: A semiconductor package in which solder balls can be loaded on an encapsulated resin to reduce the package area and a method for producing the semiconductor package. An apparatus for carrying out the method includes a first insulating substrate 5 carrying a mounting portion 3 for mounting a semiconductor device 2 and a first electrically conductive pattern 4 electrically connected to the semiconductor device 2, a sidewall section 6 formed upright around the mounting portion of the first insulating substrate, a cavity 7 defined by the first insulating substrate 5 and the sidewall section and encapsulated by an encapsulating resin 12 as the semiconductor device 2 is mounted on the mounting portion 3 and a second insulating substrate 10 provided in the cavity 7 and on the sidewall section 6 and carrying a second electrically conductive pattern 31 electrically connected to the first electrically conductive pattern 4 via plated through-holes 26 formed in the sidewall section 6.
    Type: Grant
    Filed: July 5, 2001
    Date of Patent: February 21, 2006
    Assignee: Sony Corporation
    Inventor: Mutsuyoshi Ito
  • Patent number: 6541308
    Abstract: A process for producing a semiconductor package and a structure thereof are provided in that yield per unit wafer is increased, yield and reliability are improved, and the number of production steps are decreased. The process includes the steps of a step of forming a bump on a semiconductor wafer for respective semiconductor chip constituting a semiconductor package; a step of dicing a substrate, which has been prepared, into a substrate piece corresponding to the respective semiconductor chip; a step of die-boding the substrate piece, which has been diced, on the semiconductor wafer with making the bump to correspond to the respective semiconductor chip; a step of sealing a gap between the semiconductor wafer and the substrate piece, which have been die-bonded, with a resin; and a step of dicing the semiconductor wafer and the substrate piece, which have been sealed with the resin, into the respective semiconductor package.
    Type: Grant
    Filed: September 1, 1999
    Date of Patent: April 1, 2003
    Assignee: Sony Corporation
    Inventors: Mutsuyoshi Ito, Kentaro Ohta
  • Publication number: 20020043705
    Abstract: To provide a semiconductor device and its manufacturing method capable of enhancing the mounting strength.
    Type: Application
    Filed: December 6, 2001
    Publication date: April 18, 2002
    Inventors: Mutsuyoshi Ito, Hisao Ogura, Kentaro Ohta, Kazuhiko Ishino
  • Publication number: 20020020916
    Abstract: A semiconductor package in which solder balls can be loaded on an encapsulated resin to reduce the package area and a method for producing the semiconductor package. An apparatus for carrying out the method includes a first insulating substrate 5 carrying a mounting portion 3 for mounting a semiconductor device 2 and a first electrically conductive pattern 4 electrically connected to the semiconductor device 2, a sidewall section 6 formed upright around the mounting portion of the first insulating substrate, a cavity 7 defined by the first insulating substrate 5 and the sidewall section and encapsulated by an encapsulating resin 12 as the semiconductor device 2 is mounted on the mounting portion 3 and a second insulating substrate 10 provided in the cavity 7 and on the sidewall section 6 and carrying a second electrically conductive pattern 31 electrically connected to the first electrically conductive pattern 4 via plated through-holes 26 formed in the sidewall section 6.
    Type: Application
    Filed: July 5, 2001
    Publication date: February 21, 2002
    Inventor: Mutsuyoshi Ito
  • Publication number: 20020001966
    Abstract: A process for producing a semiconductor package and a structure thereof are provided in that yield per unit wafer is increased, yield and reliability are improved, and the number of production steps are decreased. The process includes the steps of a step of forming a bump on a semiconductor wafer for respective semiconductor chip constituting a semiconductor package; a step of dicing a substrate, which has been prepared, into a substrate piece corresponding to the respective semiconductor chip; a step of die-boding the substrate piece, which has been diced, on the semiconductor wafer with making the bump to correspond to the respective semiconductor chip; a step of sealing a gap between the semiconductor wafer and the substrate piece, which have been die-bonded, with a resin; and a step of dicing the semiconductor wafer and the substrate piece, which have been sealed with the resin, into the respective semiconductor package.
    Type: Application
    Filed: September 1, 1999
    Publication date: January 3, 2002
    Inventors: MUTSUYOSHI ITO, KENTARO OHTA