Abstract: A slurry composition for a chemical mechanical polishing process and a method of manufacturing a semiconductor memory device using the slurry composition are provided. The slurry composition may include about 0.001 percent by weight to about 5 percent by weight of a ceria abrasive, about 0.001 percent by weight to about 0.1 percent by weight of a nonionic surfactant adsorbed onto a polysilicon layer forming a passivation layer on the polysilicon layer, the nonionic surfactant having a chemical structure of a triblock copolymer including a first polyethylene oxide block, a polypropylene oxide block and a second polyethylene oxide block and a remainder of water.

Abstract: A slurry composition for a chemical mechanical polishing process and a method of manufacturing a semiconductor memory device using the slurry composition are provided. The slurry composition may include about 0.001 percent by weight to about 5 percent by weight of a ceria abrasive, about 0.001 percent by weight to about 0.1 percent by weight of a nonionic surfactant adsorbed onto a polysilicon layer forming a passivation layer on the polysilicon layer, the nonionic surfactant having a chemical structure of a triblock copolymer including a first polyethylene oxide block, a polypropylene oxide block and a second polyethylene oxide block and a remainder of water.

Abstract: A slurry composition for a chemical mechanical polishing process and a method of manufacturing a semiconductor memory device using the slurry composition are provided. The slurry composition may include about 0.001 percent by weight to about 5 percent by weight of a ceria abrasive, about 0.001 percent by weight to about 0.1 percent by weight of a nonionic surfactant adsorbed onto a polysilicon layer forming a passivation layer on the polysilicon layer, the nonionic surfactant having a chemical structure of a triblock copolymer including a first polyethylene oxide block, a polypropylene oxide block and a second polyethylene oxide block and a remainder of water.

Abstract: Methods of fabricating semiconductor devices are provided. An interlayer insulating layer is provided on a single crystalline semiconductor substrate. A single crystalline semiconductor plug is provided that extends through the interlayer insulating layer and a molding layer pattern is provided on the semiconductor substrate and the single crystalline semiconductor plug. The molding layer pattern defines an opening therein that at least partially exposes a portion of the single crystalline semiconductor plug. A single crystalline semiconductor epitaxial pattern is provided on the exposed portion of single crystalline semiconductor plug using a selective epitaxial growth technique that uses the exposed portion of the single crystalline semiconductor plug as a seed layer. A single crystalline semiconductor region is provided in the opening. The single crystalline semiconductor region includes at least a portion of the single crystalline semiconductor epitaxial pattern.

Abstract: A method of forming a gate structure of a semiconductor device includes forming a gate insulation film and a polysilicon film on a semiconductor substrate where an active region and a field region are defined, followed by forming a buffer layer on the polysilicon film to minimize damage to the polysilicon film during a subsequent ion implantation process. The polysilicon film is made electrically conductive by the implanting of impurities into the polysilicon film. Gate patterns are then formed by etching the conductive polysilicon film and the gate insulation film. Defects, such as active pitting, associated with dual electrodes are effectively prevented because the polysilicon film is protected during the ion implanting process.

Abstract: Methods of fabricating semiconductor devices are provided. An interlayer insulating layer is provided on a single crystalline semiconductor substrate. A single crystalline semiconductor plug is provided that extends through the interlayer insulating layer and a molding layer pattern is provided on the semiconductor substrate and the single crystalline semiconductor plug. The molding layer pattern defines an opening therein that at least partially exposes a portion of the single crystalline semiconductor plug. A single crystalline semiconductor epitaxial pattern is provided on the exposed portion of single crystalline semiconductor plug using a selective epitaxial growth technique that uses the exposed portion of the single crystalline semiconductor plug as a seed layer. A single crystalline semiconductor region is provided in the opening. The single crystalline semiconductor region includes at least a portion of the single crystalline semiconductor epitaxial pattern.

Abstract: A method of forming a gate structure of a semiconductor device includes forming a gate insulation film and a polysilicon film on a semiconductor substrate where an active region and a field region are defined, followed by forming a buffer layer on the polysilicon film to minimize damage to the polysilicon film during a subsequent ion implantation process. The polysilicon film is made electrically conductive by the implanting of impurities into the polysilicon film. Gate patterns are then formed by etching the conductive polysilicon film and the gate insulation film. Defects, such as active pitting, associated with dual electrodes are effectively prevented because the polysilicon film is protected during the ion implanting process.