Abstract: A processor includes a first architectural register configured to store first data based on a result of executing an instruction in a first loop, the first architectural register being mapped to one of a plurality of physical registers; and a control unit configured to determine, before execution of the instruction in an n-th loop (n being a natural number greater than 1), at least one of whether the first data stored in the first architectural register is changed and whether a physical register, among the plurality of physical registers, to which the first architectural register is mapped is changed, and, based on a result of determination, execute the instruction in the n-th loop.