Patents by Inventor Myeong-Cheol Kim
Myeong-Cheol Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9741854Abstract: There is provided a method for manufacturing a semiconductor device including a substrate including a plurality of active regions, a plurality of gate electrodes extending in a first direction to intersect a portion of the plurality of active regions, and including first and second gate electrodes disposed to be adjacent to each other in the first direction, a gate isolation portion disposed between the first and second gate electrodes. The gate isolation portion includes a first layer and second layers disposed on both ends of the first layer in a second direction perpendicular to the first direction.Type: GrantFiled: December 4, 2015Date of Patent: August 22, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Keun Hee Bai, Kyoung Hwan Yeo, Seung Seok Ha, Seung Ju Park, Do Hyoung Kim, Myeong Cheol Kim, Jae Hyoung Koo, Ki Byung Park
-
Patent number: 9653363Abstract: Provided are a semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a first active fin and a second active fin which protrude from a substrate and extend along a first direction, a first gate structure which is on the first active fin to extend along a second direction intersecting the first direction, a second gate structure which is located adjacent to the first gate structure in the second direction and is on the second active fin to extend along the second direction, and a dummy structure which is in a space between the first gate structure and the second gate structure.Type: GrantFiled: May 27, 2016Date of Patent: May 16, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Bok-Young Lee, Jeong-Yun Lee, Dong-Hyun Kim, Myeong-Cheol Kim, Dong-Woo Han
-
Patent number: 9627542Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.Type: GrantFiled: May 2, 2016Date of Patent: April 18, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byoung-Ho Kwon, Cheol Kim, Ho-Young Kim, Se-Jung Park, Myeong-Cheol Kim, Bo-Kyeong Kang, Bo-Un Yoon, Jae-Kwang Choi, Si-Young Choi, Suk-Hoon Jeong, Geum-Jung Seong, Hee-Don Jeong, Yong-Joon Choi, Ji-Eun Han
-
Publication number: 20170040328Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.Type: ApplicationFiled: October 25, 2016Publication date: February 9, 2017Inventors: Hong-bae PARK, Ja-hum KU, Myeong-cheol KIM, Jin-wook LEE, Sung-kee HAN
-
Publication number: 20160358925Abstract: A semiconductor device includes a substrate, a fin active region pattern on the substrate, the fin active region pattern including an upper region and a lower region, a device isolation layer pattern surrounding the fin active region pattern, a gate pattern on the upper region of the fin active region pattern, and a stressor on the lower region of the fin active region pattern, wherein a top surface of the device isolation layer pattern is lower than a top surface of the upper region and higher than a top surface of the lower region.Type: ApplicationFiled: March 30, 2016Publication date: December 8, 2016Inventors: Keun-hee BAI, Myeong-cheol KIM, Kwan-heum LEE, Do-hyoung KIM, Jin-wook LEE, Seung-mo HA, Dong-Hoon KHANG
-
Patent number: 9508727Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.Type: GrantFiled: September 14, 2015Date of Patent: November 29, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hong-bae Park, Ja-hum Ku, Myeong-cheol Kim, Jin-wook Lee, Sung-kee Han
-
Patent number: 9508644Abstract: A method of forming a pattern includes forming a mask pattern on a substrate; etching the substrate by deep reactive ion etching (DRIE) and by using the mask pattern as an etch mask; partially removing the mask pattern to expose a portion of an upper surface of the substrate; and etching the exposed portion of the upper surface of the substrate. In the method, when a pattern is formed by DRIE, an upper portion of the pattern does not protrude or scarcely protrudes, and scallops of a sidewall of the pattern are smooth, and thus a conformal material layer may be easily formed on a surface of the pattern.Type: GrantFiled: November 2, 2015Date of Patent: November 29, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-kwon Kim, Ki-il Kim, Ah-young Cheon, Myeong-cheol Kim, Yong-jin Kim
-
Patent number: 9484458Abstract: A fabricating method of a semiconductor device includes providing a substrate having a first region and a second region, forming a plurality of first gates in the first region of the substrate, such that the first gates are spaced apart from each other at a first pitch, forming a plurality of second gates in the second region of the substrate, such that the second gates are spaced apart from each other at a second pitch different from the first pitch, implanting an etch rate adjusting dopant into the second region to form implanted regions, while blocking the first region, forming a first trench by etching the first region between the plurality of first gates, and forming a second trench by etching the second region between the plurality of second gates.Type: GrantFiled: January 22, 2015Date of Patent: November 1, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jin-Wook Lee, Myeong-Cheol Kim, Sang-Min Lee, Young-Ju Park, Hyung-Yong Kim, Myung-Hoon Jung
-
Publication number: 20160315018Abstract: Provided are a semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a first active fin and a second active fin which protrude from a substrate and extend along a first direction, a first gate structure which is on the first active fin to extend along a second direction intersecting the first direction, a second gate structure which is located adjacent to the first gate structure in the second direction and is on the second active fin to extend along the second direction, and a dummy structure which is in a space between the first gate structure and the second gate structure.Type: ApplicationFiled: May 27, 2016Publication date: October 27, 2016Inventors: Bok-Young LEE, Jeong-Yun LEE, Dong-Hyun KIM, Myeong-Cheol KIM, Dong-Woo HAN
-
Publication number: 20160247925Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.Type: ApplicationFiled: May 2, 2016Publication date: August 25, 2016Inventors: Byoung-Ho KWON, Cheol KIM, Ho-Young KIM, Se-Jung PARK, Myeong-Cheol KIM, Bo-Kyeong KANG, Bo-Un YOON, Jae-Kwang CHOI, Si-Young CHOI, Suk-Hoon JEONG, Geum-Jung SEONG, Hee-Don JEONG, Yong-Joon CHOI, Ji-Eun HAN
-
Patent number: 9401359Abstract: A method of manufacturing a semiconductor device includes forming a gate structure through a first insulating interlayer on a substrate such that the gate structure includes a spacer on a sidewall thereof, forming a first hard mask on the gate structure, partially removing the first insulating interlayer using the first hard mask as an etching mask to form a first contact hole such that the first contact hole exposes a top surface of the substrate, forming a metal silicide pattern on the top surface of the substrate exposed by the first contact hole, and forming a plug electrically connected to the metal silicide pattern.Type: GrantFiled: November 25, 2014Date of Patent: July 26, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Soo-Yeon Jeong, Myeong-Cheol Kim, Do-Hyoung Kim, Do-Haing Lee, Nam-Myun Cho, In-Ho Kim
-
Patent number: 9379107Abstract: Provided are a semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a first active fin and a second active fin which protrude from a substrate and extend along a first direction, a first gate structure which is on the first active fin to extend along a second direction intersecting the first direction, a second gate structure which is located adjacent to the first gate structure in the second direction and is on the second active fin to extend along the second direction, and a dummy structure which is in a space between the first gate structure and the second gate structure.Type: GrantFiled: April 22, 2015Date of Patent: June 28, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Bok-Young Lee, Jeong-Yun Lee, Dong-Hyun Kim, Myeong-Cheol Kim, Dong-Woo Han
-
Publication number: 20160181425Abstract: There is provided a method for manufacturing a semiconductor device including a substrate including a plurality of active regions, a plurality of gate electrodes extending in a first direction to intersect a portion of the plurality of active regions, and including first and second gate electrodes disposed to be adjacent to each other in the first direction, a gate isolation portion disposed between the first and second gate electrodes. The gate isolation portion includes a first layer and second layers disposed on both ends of the first layer in a second direction perpendicular to the first direction.Type: ApplicationFiled: December 4, 2015Publication date: June 23, 2016Inventors: Keun Hee BAI, Kyoung Hwan YEO, Seung Seok HA, Seung Ju PARK, Do Hyoung KIM, Myeong Cheol KIM, Jae Hyoung KOO, Ki Byung PARK
-
Publication number: 20160133632Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.Type: ApplicationFiled: September 14, 2015Publication date: May 12, 2016Inventors: Hong-bae PARK, Ja-hum KU, Myeong-cheol KIM, Jin-wook LEE, Sung-kee HAN
-
Patent number: 9312478Abstract: Magnetic devices, and methods of manufacturing the same, include a stack structure including at least one magnetic layer, etched using an etching gas including at least 70 volume percent of a hydrogen-containing gas and at least 2 volume percent of CO gas.Type: GrantFiled: August 20, 2012Date of Patent: April 12, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Hak-sun Lee, Tokashiki Ken, Myeong-cheol Kim, Hyung-joon Kwon, Sang-min Lee, Woo-cheol Lee, Myung-hoon Jung
-
Patent number: 9305921Abstract: A semiconductor device including: a first gate pattern disposed in a peripheral region of a substrate; a second gate pattern disposed in a cell region of the substrate; a first insulator formed on sidewalls of the first gate pattern; and a second insulator formed on sidewalls of the second gate pattern, wherein a dielectric constant of the first insulator is different from a dielectric constant of the second insulator, and wherein a height of the second insulator is greater than a height of the second gate pattern.Type: GrantFiled: December 10, 2014Date of Patent: April 5, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Chan Lee, Seung-Jae Lee, Sang-Bom Kang, Dae-Young Kwak, Myeong-Cheol Kim, Yong-Ho Jeon
-
Patent number: 9299811Abstract: Semiconductor devices may include first and second fins that protrude from a substrate, extend in a first direction, and are separated from each other in the first direction. Semiconductor devices may also include a field insulating layer that is disposed between the first and second fins to extend in a second direction intersecting the first direction, an etch-stop layer pattern that is formed on the field insulating layer and a dummy gate structure that is formed on the etch-stop layer pattern.Type: GrantFiled: October 21, 2014Date of Patent: March 29, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Wook-Je Kim, Jae-Yup Chung, Jong-Seo Hong, Cheol Kim, Hee-Soo Kang, Hyun-Jo Kim, Hee-Don Jeong, Soo-Hun Hong, Sang-Bom Kang, Myeong-Cheol Kim, Young-Su Chung
-
Patent number: 9287161Abstract: A method of manufacturing a wiring includes sequentially forming a first insulation layer, a first layer, and a second layer on a substrate, etching an upper portion of the second layer a plurality of times to form a second layer pattern including a first recess having a shape of a staircase, etching a portion of the second layer pattern and a portion of the first layer under the first recess to form a first layer pattern including a second recess having a shape of a staircase similar to the first recess, etching a portion of the first layer pattern under the second recess to form a first opening exposing a portion of a top surface of the first insulation layer, etching the exposed portion of the first insulation layer to form a second opening through the first insulation layer, and forming a wiring filling the second opening.Type: GrantFiled: September 26, 2014Date of Patent: March 15, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Hyun Lee, Myeong-Cheol Kim, Yoo-Jung Lee, Il-Sup Kim, Seung-Ju Park
-
Publication number: 20160064380Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.Type: ApplicationFiled: November 5, 2015Publication date: March 3, 2016Inventors: Byoung-Ho KWON, Cheol KIM, Ho-Young KIM, Se-Jung PARK, Myeong-Cheol KIM, Bo-Kyeong KANG, Bo-Un YOON, Jae-Kwang CHOI, Si-Young CHOI, Suk-Hoon JEONG, Geum-Jung SEONG, Hee-Don JEONG, Yong-Joon CHOI, Ji-Eun HAN
-
Publication number: 20160056110Abstract: A method of forming a pattern includes forming a mask pattern on a substrate; etching the substrate by deep reactive ion etching (DRIE) and by using the mask pattern as an etch mask; partially removing the mask pattern to expose a portion of an upper surface of the substrate; and etching the exposed portion of the upper surface of the substrate. In the method, when a pattern is formed by DRIE, an upper portion of the pattern does not protrude or scarcely protrudes, and scallops of a sidewall of the pattern are smooth, and thus a conformal material layer may be easily formed on a surface of the pattern.Type: ApplicationFiled: November 2, 2015Publication date: February 25, 2016Inventors: Dong-kwon Kim, Ki-il Kim, Ah-young Cheon, Myeong-cheol Kim, Yong-jin Kim