Abstract: Disclosed herein are methods and apparatuses for producing hydrogen and oxygen from water, or for producing less-complex constituents from a more-complex compound, more particularly, for decomposing chemical bonds of a compound using resonant electromagnetic (EM) waves such as sunlight.

Abstract: Disclosed herein is a method and apparatus for producing hydrogen and oxygen from water, more particularly, for decomposing water molecular bonds using resonant waves. The produced hydrogen gas may be used as a fuel, and the released oxygen gas may be used as an oxidant.

Abstract: A battery cell array includes a plurality of battery banks, each battery bank including a two-dimensional m-by-n or higher-order matrix of battery cells; a row address decoder configured to activate selected address lines, the address lines including a wordline(s); a column address decoder configured to activate selected address lines, the address lines including a bitline(s); an address decoder(s), if required, configured to activate a select signal(s) to select an additional address line(s) for a more than two-dimensional matrix of battery cells; a controller configured to directly or indirectly activate a bank select signal(s) to select a battery bank of the plurality of battery banks.

Abstract: A battery management system includes several blocks: a battery cell array comprising a plurality of battery cells; a charger selector array connected electrically to the battery cell array to charge the battery cells; an analyzer array configured to monitor a condition or status of the battery cells and report the condition or status of the battery cells; a battery output array connected electrically to the battery cell array to provide electric power out of the battery cells; and a controller configured to control charge movement and command flow among the blocks in the battery system such as charger selector array and the battery output array according to the reported condition or status from the analyzer array.

Abstract: A battery cell array includes a plurality of battery banks, each battery bank including a two-dimensional m-by-n or higher-order matrix of battery cells; a row address decoder configured to activate selected address lines, the address lines including a wordline(s); a column address decoder configured to activate selected address lines, the address lines including a bitline(s); an address decoder(s), if required, configured to activate a select signal(s) to select an additional address line(s) for a more than two-dimensional matrix of battery cells; a controller configured to directly or indirectly activate a bank select signal(s) to select a battery bank of the plurality of battery banks.

Abstract: A battery management system includes several blocks: a battery cell array comprising a plurality of battery cells; a charger selector array connected electrically to the battery cell array to charge the battery cells; an analyzer array configured to monitor a condition or status of the battery cells and report the condition or status of the battery cells; a battery output array connected electrically to the battery cell array to provide electric power out of the battery cells; and a controller configured to control charge movement and command flow among the blocks in the battery system such as charger selector array and the battery output array according to the reported condition or status from the analyzer array.

Abstract: A data storage device includes a processor and a non-volatile memory. The processor compares a data processing size of a first command received from the host at a first time point with a reference size and divides the first command into a plurality of sub-commands when the data processing size is greater than the reference size. The data storage device further includes a memory that includes a first queue and a second queue.

Abstract: A storage device includes a storage medium and a controller configured to control the storage medium. The controller includes an interface unit configured to interface with a host, a processing unit connected to the interface unit via a first signal line and configured to process a direct load operation and a direct store operation between the host and the controller, and at least one memory connected to the interface unit via a second signal line. The at least one memory is configured to temporarily store data read from the storage medium or data received from the host, and is configured to be directly accessed by the host.

Abstract: A storage device includes a storage medium and a controller configured to control the storage medium. The controller includes an interface unit configured to interface with a host, a processing unit connected to the interface unit via a first signal line and configured to process a direct load operation and a direct store operation between the host and the controller, and at least one memory connected to the interface unit via a second signal line. The at least one memory is configured to temporarily store data read from the storage medium or data received from the host, and is configured to be directly accessed by the host.

Abstract: A data storage device includes a processor and a non-volatile memory. The processor compares a data processing size of a first command received from the host at a first time point with a reference size and divides the first command into a plurality of sub-commands when the data processing size is greater than the reference size. The data storage device further includes a memory that includes a first queue and a second queue.

Abstract: A storage device includes a storage medium and a controller configured to control the storage medium. The controller includes an interface unit configured to interface with a host, a processing unit connected to the interface unit via a first signal line and configured to process a direct load operation and a direct store operation between the host and the controller, and at least one memory connected to the interface unit via a second signal line. The at least one memory is configured to temporarily store data read from the storage medium or data received from the host, and is configured to be directly accessed by the host.

Abstract: Disclosed is a low power latch that includes a low threshold voltage (LThV) inverter inverting an input data value to provide an output data value and including a LThV pull-up transistor and LThV pull-down transistor that operate at a threshold voltage less than a reference threshold voltage. The low power latch also includes a high threshold voltage (HThV) transistor isolating unit configured to isolate a power supply voltage provided to the LThV inverter during a sleep mode indicated by a sleep mode signal, and including a first HThV transistor and a second HThV transistor that operate at a threshold voltage less than the reference threshold voltage.

Abstract: Methods and apparatus for estimating the propagation delay along a logical signal path are described herein. The methods and apparatus account for the behavior of multi-stage logic gates along a signal path, initial input transition times, inter-stage fanouts, as well as different logic gate types. The methods and apparatus convert signal transition features into an effective fanout to provide estimates of gate delay dependencies on input slope and gate logic topology.

Abstract: Methods and apparatus for estimating the propagation delay along a logical signal path are described herein. The methods and apparatus account for the behavior of multi-stage logic gates along a signal path, initial input transition times, inter-stage fanouts, as well as different logic gate types. The methods and apparatus convert signal transition features into an effective fanout to provide estimates of gate delay dependencies on input slope and gate logic topology.

Abstract: The data processing system, a combination of multithreaded architecture and a VLIW (Very Long Instruction Word) processor is adapted to process plural threads. The system uses multiple program counters for context-switching only a subinstruction which causes a long latency. A method is provided for processing instructions in a data processing system having an active thread block, a ready thread block and a waiting thread block, and a instruction execution block, for processing a plurality of threads. The method includes combining instructions issued from the respective active threads into one new instruction, each active thread having a plurality of instructions, and the issued instructions being used as subinstructions in the combined one instruction. The combined instruction as processed by the instruction execution block, while tracing contexts relating to the threads which provide the respective subinstructions by using multiple program counters.