Patents by Inventor Myil RAMKUMAR

Myil RAMKUMAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • HARDWARE MANAGED POWER COLLAPSE AND CLOCK WAKE-UP FOR MEMORY MANAGEMENT UNITS AND DISTRIBUTED VIRTUAL MEMORY NETWORKS
    Publication number: 20190324512
    Abstract: Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.
    Type: Application
    Filed: July 1, 2019
    Publication date: October 24, 2019
    Inventors: Jason Edward PODAIMA, Christophe Denis Bernard AVOINNE, Manokanthan SOMASUNDARAM, Sina DENA, Paul Christopher John WIERCIENSKI, Bohuslav RYCHLIK, Steven John HALTER, Jaya Prakash SUBRAMANIAM GANASAN, Myil RAMKUMAR, Dipti Ranjan PAL
  • Hardware managed power collapse and clock wake-up for memory management units and distributed virtual memory networks
    Patent number: 10386904
    Abstract: Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: August 20, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Jason Edward Podaima, Christophe Denis Bernard Avoinne, Manokanthan Somasundaram, Sina Dena, Paul Christopher John Wiercienski, Bohuslav Rychlik, Steven John Halter, Jaya Prakash Subramaniam Ganasan, Myil Ramkumar, Dipti Ranjan Pal
  • Bandwidth/resource management for multithreaded processors
    Patent number: 10102031
    Abstract: Systems and methods relate to managing shared resources in a multithreaded processor comprising two or more processing threads. Danger levels for the two or more threads are determined, wherein the danger level of a thread is based on a potential failure of the thread to meet a deadline due to unavailability of a shared resource. Priority levels associated with the two or more threads are also determined, wherein the priority level is higher for a thread whose failure to meet a deadline is unacceptable and the priority level is lower for a thread whose failure to meet a deadline is acceptable. The two or more threads are scheduled based at least on the determined danger levels for the two or more threads and priority levels associated with the two or more threads.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: October 16, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Serag Monier Gadelrab, Christopher Edward Koob, Simon Booth, Aris Balatsos, Johnny Jone Wai Kuan, Myil Ramkumar, Bhupinder Singh Pabla, Sean David Sweeney, George Patsilaras
  • HARDWARE MANAGED POWER COLLAPSE AND CLOCK WAKE-UP FOR MEMORY MANAGEMENT UNITS AND DISTRIBUTED VIRTUAL MEMORY NETWORKS
    Publication number: 20170285705
    Abstract: Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.
    Type: Application
    Filed: March 31, 2016
    Publication date: October 5, 2017
    Inventors: Jason Edward PODAIMA, Christophe Denis Bernard AVOINNE, Manokanthan SOMASUNDARAM, Sina DENA, Paul Christopher John WIERCIENSKI, Bohuslav RYCHLIK, Steven John HALTER, Jaya Prakash SUBRAMANIAM GANASAN, Myil RAMKUMAR, Dipt Ranjan PAL
  • BANDWIDTH/RESOURCE MANAGEMENT FOR MULTITHREADED PROCESSORS
    Publication number: 20160350152
    Abstract: Systems and methods relate to managing shared resources in a multithreaded processor comprising two or more processing threads. Danger levels for the two or more threads are determined, wherein the danger level of a thread is based on a potential failure of the thread to meet a deadline due to unavailability of a shared resource. Priority levels associated with the two or more threads are also determined, wherein the priority level is higher for a thread whose failure to meet a deadline is unacceptable and the priority level is lower for a thread whose failure to meet a deadline is acceptable. The two or more threads are scheduled based at least on the determined danger levels for the two or more threads and priority levels associated with the two or more threads.
    Type: Application
    Filed: September 25, 2015
    Publication date: December 1, 2016
    Inventors: Serag Monier GADELRAB, Christopher Edward KOOB, Simon BOOTH, Aris BALATSOS, Johnny Jone Wai KUAN, Myil RAMKUMAR, Bhupinder Singh PABLA, Sean David SWEENEY, George PATSILARAS