Abstract: The programmable timer for use in a microprocessor has a counter and a reset register each connected to a databus of the microprocessor, and a first comparator for comparing the counter against the reset register in providing the result of the comparison at a first comparison output. The counter includes a clock signal input for counting clock pulses. The counter may be reset to a reset value via a reset input provided on the counter. The reset register may receive and store a digital value from the microprocessor. The first comparison output is connected to the reset input in order to reset the counter when the counter reaches a count greater than or equal to the value stored in the reset register thereby providing a periodic signal at the first comparison output. The programmable timer may operate in various modes including, an interval timing mode, a PWM encode mode and a pulse timing mode.

Abstract: A central processing unit having at least one memory for storing instructions and data includes a program counter for storing program counter values. An execution unit retrieves and processes instructions located in the memory at addresses corresponding to the contents of the program counter. Multiple stacks independent of the memory are provided for storing program counter values. A multiplexer connects the program counter to each stack. A stack select register connected to a control input of the multiplexer enables the transfer of program counter values between the program counter and one of the stacks indicated by the contents of the stack select register. The central processing unit provides an efficient multi-tasking capability since the program counter state of each task can be stored in one of the multiple stacks.