Patents by Inventor Mylene ROUSSELLET
Mylene ROUSSELLET has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240313942Abstract: Provided is a method for securing against side channel attacks. An elliptic curve cryptographic process comprises a multiple points multiplication operation using predetermined scalar values, Pi being points of an elliptic curve over a finite field defined by parameters (F, E, G, N) together with the point addition law where F is a field over which is defined the curve, E is an equation of the curve, G is a base point in E over F and N is the order of the base point G. The method comprises generating (S1) a masking value iRand, multiplicatively masking (S2) each predetermined scalar value di with said generated masking value iRand to obtain masked scalars di?, computing (S3) a masked multiple points multiplication operation result, and obtaining (S4) said multiple points multiplication operation result R by unmasking said masked multiple points multiplication operation result R?.Type: ApplicationFiled: January 11, 2022Publication date: September 19, 2024Applicant: THALES DIS FRANCE SASInventors: David VIGILANT, Steven MADEC, Mylène ROUSSELLET
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Publication number: 20240031130Abstract: Provided is a method for securing against high-order side-channel attacks wherein a substep of field inversion is performed by a cryptographic device. The method includes computing (S1) a Dirac output value, adding (S2) said Dirac output value to one of said shares of the first set of shares to obtain a second set of shares, performing a conversion of the second set of shares (S3) from said (n+1) additive sharing to a (n+1)-multiplicative sharing, performing an inversion of each share of the (n+1)-multiplicative sharing (S4), performing a conversion of the inverted shares (S5) from said multiplicative sharing to a (n+1)-additive sharing to obtain a third set of shares, and adding (S6) said Dirac output value to one of said shares of the third set of shares. Other embodiments disclosed.Type: ApplicationFiled: December 14, 2021Publication date: January 25, 2024Applicant: THALES DIS FRANCE SASInventors: Mylène ROUSSELLET, David VIGILANT, Olivier ADJONYO KOFFI BENIT
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Patent number: 11281433Abstract: The present invention relates to a method for generating a prime number and using it in a cryptographic application, comprising the steps of: a) determining at least one binary base B with a small size b=log2(B) bits and for each determined base B at least one small prime pi such that B mod pi=1, with i an integer, b) selecting a prime candidate YP, c) decomposing the selected prime candidate YP in a base B selected among said determined binary bases : YP=?yjBid) computing a residue yPB from the candidate YP for said selected base such that yPB=?yje) testing if said computed residue yPB is divisible by one small prime pi selected among said determined small primes for said selected base B, f) while said computed residue yPB is not divisible by said selected small prime, iteratively repeating above step e) until tests performed at step e) prove that said computed residue yPB is not divisible by any of said determined small primes for said selected base B, g) when said computed residue yPB is not divisible by aType: GrantFiled: February 9, 2018Date of Patent: March 22, 2022Assignee: THALES DIS FRANCE SAInventors: Alexandre Berzati, Myléne Roussellet
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Publication number: 20200057611Abstract: The present invention relates to a method for generating a prime number and using it in a cryptographic application, comprising the steps of: a) determining at least one binary base B with a small size b=log2(B) bits and for each determined base B at least one small prime pi such that B mod pi=1, with i an integer, b) selecting a prime candidate YP, c) decomposing the selected prime candidate YP in a base B selected among said determined binary bases : YP=?yjBid) computing a residue yPB from the candidate YP for said selected base such that yPB=?yje) testing if said computed residue yPB is divisible by one small prime pi selected among said determined small primes for said selected base B, f) while said computed residue yPB is not divisible by said selected small prime, iteratively repeating above step e) until tests performed at step e) prove that said computed residue yPB is not divisible by any of said determined small primes for said selected base B, g) when said computed residue yPB is not divisible by aType: ApplicationFiled: February 9, 2018Publication date: February 20, 2020Inventors: Alexandre BERZATI, Myléne ROUSSELLET
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Patent number: 9977899Abstract: In an aspect, a method can include generating a cyclic redundancy check code for a binary data item, using a generator polynomial; and masking, using polynomial addition, the binary data item with a binary mask. The method can also include at least one of: storing, by a microcircuit, the masked binary data item in a memory of an electronic device; or transferring, by the microcircuit, the masked data item to another device. The cyclic redundancy check code for the binary data item can be generated from the masked binary data item to prevent discovery of the binary data item by a side-channel attack during the generating the cyclic redundancy check. The binary mask can be a multiple of a random number and the generator polynomial, such that respective cyclic redundancy check code of the masked data item and the binary data item have a same result.Type: GrantFiled: March 26, 2013Date of Patent: May 22, 2018Assignee: Inside SecureInventors: Mylène Roussellet, Vincent Verneuil
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Publication number: 20150082435Abstract: The present invention relates to a method for processing a binary data item, comprising a step of calculating a cyclic redundancy check code for the data item by means of a generator polynomial, wherein the step of calculating the cyclic redundancy check code comprises the steps of: masking the data item with a random binary mask that is a multiple of the generator polynomial, and generating the cyclic redundancy check code for the data item from the masked data item.Type: ApplicationFiled: March 26, 2013Publication date: March 19, 2015Applicant: INSIDE SECUREInventors: Mylène Roussellet, Vincent Verneuil
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Publication number: 20140351603Abstract: The invention relates to a symmetric encryption process executed by a microcircuit to transform a message into an encrypted message from a secret key, the process including a first round, intermediary rounds, and a last round. According to the invention, the process includes several executions of the first round and of the last round, and a number of executions of at least one intermediary round, the number of executions being less than the number of executions of the first and last rounds. The invention is particularly applicable to DES, Triple DES, and AES processes.Type: ApplicationFiled: December 21, 2012Publication date: November 27, 2014Inventors: Benoît Feix, Mylène Roussellet
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Patent number: 8572406Abstract: An integrated circuit including a multiplication function configured to execute a multiplication operation of two binary words x and y including a plurality of basic multiplication steps of components xi of word x by components yj of word y is described. The multiplication function of the integrated circuit is configured to execute two successive multiplications by modifying, in a random or pseudo-random manner, an order in which the basic multiplication steps of components xi by components yj are executed.Type: GrantFiled: March 31, 2010Date of Patent: October 29, 2013Assignee: Inside ContactlessInventors: Benoit Feix, Georges Gagnerot, Mylène Roussellet, Vincent Verneuil
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Patent number: 8457919Abstract: A process for testing an integrated circuit includes collecting a set of points of a physical property while the integrated circuit is executing a multiplication, dividing the set of points into a plurality subsets of lateral points, calculating an estimation of the value of the physical property for each subset, and applying to the subset of lateral points a step of horizontal transversal statistical processing by using the estimations of the value of the physical property, to verify a hypothesis about the variables manipulated by the integrated circuit.Type: GrantFiled: March 31, 2010Date of Patent: June 4, 2013Assignee: Inside SecureInventors: Benoit Feix, Georges Gagnerot, Mylene Roussellet, Vincent Verneuil
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Publication number: 20120221618Abstract: A method and a device protected against hidden channel attacks includes a calculation of the result of the exponentiation of a data m by an exponent d. The method and the device are configured to execute only multiplications of identical large variables, by breaking down any multiplication of different large variables x, y into a combination of multiplications of identical large variables.Type: ApplicationFiled: February 23, 2012Publication date: August 30, 2012Applicant: INSIDE SECUREInventors: Benoît FEIX, Georges GAGNEROT, Myléne ROUSSELLET, Vincent VERNEUIL, Christophe CLAVIER
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Publication number: 20110246119Abstract: A process for testing an integrated circuit includes collecting a set of points of a physical property while the integrated circuit is executing a multiplication, dividing the set of points into a plurality subsets of lateral points, calculating an estimation of the value of the physical property for each subset, and applying to the subset of lateral points a step of horizontal transversal statistical processing by using the estimations of the value of the physical property, to verify a hypothesis about the variables manipulated by the integrated circuit.Type: ApplicationFiled: March 31, 2010Publication date: October 6, 2011Applicant: Inside ContactlessInventors: Benoit FEIX, Georges GAGNEROT, Mylene ROUSSELLET, Vincent VERNEUIL
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Publication number: 20110246789Abstract: An integrated circuit including a multiplication function configured to execute a multiplication operation of two binary words x and y including a plurality of basic multiplication steps of components xi of word x by components yj of word y is described. The multiplication function of the integrated circuit is configured to execute two successive multiplications by modifying, in a random or pseudo-random manner, an order in which the basic multiplication steps of components xi by components yj are executed.Type: ApplicationFiled: March 31, 2010Publication date: October 6, 2011Applicant: INSIDE CONTACTLESSInventors: Benoit FEIX, Georges GAGNEROT, Mylene ROUSSELLET, Vincent VERNEUIL