Patents by Inventor Myles H. Wakayama
Myles H. Wakayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8711288Abstract: An integrated communications system. A substrate having a receiver disposed on the substrate for converting a received signal to an IF signal, a digital IF demodulator disposed on the substrate and coupled to the receiver for converting the IF signal to a demodulated baseband signal, and a transmitter disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.Type: GrantFiled: September 7, 2006Date of Patent: April 29, 2014Assignee: Broadcom CorporationInventors: Pieter Vorenkamp, Myles H. Wakayama, Steven Jaffe, Frank Carr, Arnoldus Venes, Peter R. Kinget, Daniel J. Marz, Thinh Nguyen
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Patent number: 8422591Abstract: Various systems and methods related to equalization precoding in a communications channel are disclosed. In one implementation precoding is performed on signals transmitted over an optical channel. In one implementation precoding and decoding operations are performed in parallel to facilitate high speed processing in relatively low cost circuits. Initialization of the precoders may be realized by transmitting information related to the characteristics of the channel between transceiver pairs.Type: GrantFiled: April 20, 2011Date of Patent: April 16, 2013Assignee: Broadcom CorporationInventors: Oscar E. Agazzi, Gottfried Ungerboeck, Keshab K. Parhi, Christian A. Lutkemeyer, Pieter Vorenkamp, Kevin T. Chan, Myles H. Wakayama
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Publication number: 20110206109Abstract: Various systems and methods related to equalization precoding in a communications channel are disclosed. In one implementation precoding is performed on signals transmitted over an optical channel. In one implementation precoding and decoding operations are performed in parallel to facilitate high speed processing in relatively low cost circuits. Initialization of the precoders may be realized by transmitting information related to the characteristics of the channel between transceiver pairs.Type: ApplicationFiled: April 20, 2011Publication date: August 25, 2011Inventors: Oscar E. Agazzi, Gottfried Ungerboeck, Keshab K. Parhi, Christian A. Lutkemeyer, Pieter Vorenkamp, Kevin T. Chan, Myles H. Wakayama
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Patent number: 7933341Abstract: Various systems and methods related to equalization precoding in a communications channel are disclosed. In one implementation preceding is performed on signals transmitted over an optical channel. In one implementation preceding and decoding operations are performed in parallel to facilitate high speed processing in relatively low cost circuits. Initialization of the precoders may be realized by transmitting information related to the characteristics of the channel between transceiver pairs.Type: GrantFiled: February 28, 2001Date of Patent: April 26, 2011Inventors: Oscar E. Agazzi, Gottfried Ungerboeck, Keshab K. Parhi, Christian A. Lutkemeyer, Pieter Vorenkamp, Kevin T. Chan, Myles H. Wakayama
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Patent number: 7366940Abstract: A predictive time base generator having predictive synchronizer and replica delay element coupled with the synchronizer feedback delay loop. The predictive time base generator receives a clock signal delayed by a predetermined clock delay and produces a predictive time signal advanced in time by an amount represented by the replica delay element. The replica delay element can replicate one or both of a predetermined clock delay and a predetermined data delay, substantially nullifying the respective delays in critical signal paths of a device. The replica delay element can include replicas of structure(s) found in an incoming clock path and an outgoing data path, such elements including, for example, voltage level shifters, buffers or data latches, multiplexers, wire element models, and the like. A predictive computer bus interface adapter which incorporates the aforementioned predictive time base generator also is provided.Type: GrantFiled: November 17, 2004Date of Patent: April 29, 2008Assignee: Broadcom CorporationInventors: Jennifer Y. Chiao, Gary A. Alvstad, Myles H. Wakayama
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Patent number: 7106388Abstract: An integrated communications system. A substrate having a receiver disposed on the substrate for converting a received signal to an IF signal, a digital IF demodulator disposed on the substrate and coupled to the receiver for converting the IF signal to a demodulated baseband signal, and a transmitter disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.Type: GrantFiled: December 15, 2000Date of Patent: September 12, 2006Assignee: Broadcom CorporationInventors: Pieter Vorenkamp, Myles H. Wakayama, Steven Jaffe, Frank Carr, Arnoldus Venes, Peter R. Kinget, Daniel J. Marz, Thinh Nguyen
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Patent number: 7072633Abstract: A double-conversion tuner receives an RF signal having a number of channels and down-converts a selected channel from the plurality of channels. The double-conversion tuner includes a first mixer configured to up-convert the RF signal to a first IF signal using a first local oscillator signal. A first local oscillator includes a delta-sigma fractional-N phase lock loop to produce the first local oscillator signal. The delta-sigma fractional-N phase lock loop is configured to perform fine-tuning of the first local oscillator signal and to have a wide tuning range sufficient to cover the number of channels. A bandpass filter is configured to select a subset of channels from said first IF signal. A second mixer is configured to down-convert the subset of channels to a second IF signal using a second local oscillator signal. A second local oscillator generates the second local oscillator signal.Type: GrantFiled: February 14, 2003Date of Patent: July 4, 2006Assignee: Broadcom CorporationInventors: Ramon A Gomez, Myles H Wakayama
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Patent number: 7057465Abstract: A high precision charge pump used in a phase-lock-loop incorporating a phase/frequency detector is designed and constructed to substantially eliminate the effects of DC offset and glitch errors on the charge pump output current. The high precision charge pump is constructed of parallel current paths each having a central node which is, in turn, connected to a feedback element. The feedback element defines a feedback current which is applied to the charge pump so as to maintain the two central nodes at an equi-potential level and to maintain the value of the pump-down current exactly equal to the value of the pump-up current output by the device.Type: GrantFiled: April 11, 2005Date of Patent: June 6, 2006Assignee: Broadcom CorporationInventor: Myles H. Wakayama
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Patent number: 6897733Abstract: A high precision charge pump used in a phase-lock-loop incorporating a phase/frequency detector is designed and constructed to substantially eliminate the effects of DC offset and glitch errors on the charge pump output current. The high precision charge pump is constructed of parallel current paths each having a central node which is, in turn, connected to a feedback element. The feedback element defines a feedback current which is applied to the charge pump so as to maintain the two central nodes at an equi-potential level and to maintain the value of the pump-down current exactly equal to the value of the pump-up current output by the device.Type: GrantFiled: October 5, 2001Date of Patent: May 24, 2005Assignee: Broadcom CorporationInventor: Myles H. Wakayama
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Patent number: 6829715Abstract: A predictive time base generator having predictive synchronizer and replica delay element coupled with the synchronizer feedback delay loop. The predictive time base generator receives a clock signal delayed by a predetermined clock delay and produces a predictive time signal advanced in time by an amount represented by the replica delay element. The replica delay element can replicate one or both of a predetermined clock delay and a predetermined data delay, substantially nullifying the respective delays in critical signal paths of a device. The replica delay element can include replicas of structure(s) found in an incoming clock path and an outgoing data path, such elements including, for example, voltage level shifters, buffers or data latches, multiplexers, wire element models, and the like. A predictive computer bus interface adapter which incorporates the aforementioned predictive time base generator also is provided.Type: GrantFiled: May 25, 2001Date of Patent: December 7, 2004Assignee: Broadcom CorporationInventors: Jennifer Y. Chiao, Gary A. Alvstad, Myles H. Wakayama
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Publication number: 20040221144Abstract: A predictive time base generator having predictive synchronizer and replica delay element coupled with the synchronizer feedback delay loop. The predictive time base generator receives a clock signal delayed by a predetermined clock delay and produces a predictive time signal advanced in time by an amount represented by the replica delay element. The replica delay element can replicate one or both of a predetermined clock delay and a predetermined data delay, substantially nullifying the respective delays in critical signal paths of a device. The replica delay element can include replicas of structure(s) found in an incoming clock path and an outgoing data path, such elements including, for example, voltage level shifters, buffers or data latches, multiplexers, wire element models, and the like. A predictive computer bus interface adapter which incorporates the aforementioned predictive time base generator also is provided.Type: ApplicationFiled: May 25, 2001Publication date: November 4, 2004Applicant: Reel, FrameInventors: Jennifer Y. Chiao, Gary A. Alvstad, Myles H. Wakayama
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Publication number: 20030224748Abstract: A double-conversion tuner receives an RF signal having a number of channels and down-converts a selected channel from the plurality of channels. The double-conversion tuner includes a first mixer configured to up-convert the RF signal to a first IF signal using a first local oscillator signal. A first local oscillator includes a delta-sigma fractional-N phase lock loop to produce the first local oscillator signal. The delta-sigma fractional-N phase lock loop is configured to perform fine-tuning of the first local oscillator signal and to have a wide tuning range sufficient to cover the number of channels. A bandpass filter is configured to select a subset of channels from said first IF signal. A second mixer is configured to down-convert the subset of channels to a second IF signal using a second local oscillator signal. A second local oscillator generates the second local oscillator signal.Type: ApplicationFiled: February 14, 2003Publication date: December 4, 2003Applicant: Broadcom CorporationInventors: Ramon A. Gomez, Myles H. Wakayama
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Publication number: 20020050864Abstract: A high precision charge pump used in a phase-lock-loop incorporating a phase/frequency detector is designed and constructed to substantially eliminate the effects of DC offset and glitch errors on the charge pump output current. The high precision charge pump is constructed of parallel current paths each having a central node which is, in turn, connected to a feedback element. The feedback element defines a feedback current which is applied to the charge pump so as to maintain the two common drain nodes at an equi-potential level and to maintain the value of the pump-down current exactly equal to the value of the pump-up current output by the device.Type: ApplicationFiled: October 5, 2001Publication date: May 2, 2002Inventor: Myles H. Wakayama
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Publication number: 20020047942Abstract: An integrated communications system. A substrate having a receiver disposed on the substrate for converting a received signal to an IF signal, a digital IF demodulator disposed on the substrate and coupled to the receiver for converting the IF signal to a demodulated baseband signal, and a transmitter disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.Type: ApplicationFiled: December 15, 2000Publication date: April 25, 2002Inventors: Pieter Vorenkamp, Myles H. Wakayama, Steven Jaffe, Frank Carr, Arnoldus Venes, Peter R. Kinget, Daniel J. Marz, Thinh Nguyen
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Patent number: 6326852Abstract: A high precision charge pump used in a phase-lock-loop incorporating a phase/frequency detector is designed and constructed to substantially eliminate the effects of DC offset and glitch errors on the charge pump output current. The high precision charge pump is constructed of parallel current paths each having a central node which is, in turn, connected to a feedback element. The feedback element defines a feedback current which is applied to the charge pump so as to maintain the two central nodes at an equi-potential level and to maintain the value of the pump-down current exactly equal to the value of the pump-up current output by the device.Type: GrantFiled: August 28, 2000Date of Patent: December 4, 2001Assignee: Broadcom CorporationInventor: Myles H. Wakayama
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Publication number: 20010035994Abstract: Various systems and methods related to equalization precoding in a communications channel are disclosed. In one implementation preceding is performed on signals transmitted over an optical channel. In one implementation preceding and decoding operations are performed in parallel to facilitate high speed processing in relatively low cost circuits. Initialization of the precoders may be realized by transmitting information related to the characteristics of the channel between transceiver pairs.Type: ApplicationFiled: February 28, 2001Publication date: November 1, 2001Inventors: Oscar E. Agazzi, Gottfried Ungerboeck, Keshab K. Parhi, Christian A. Lutkemeyer, Pieter Vorenkamp, Kevin T. Chan, Myles H. Wakayama
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Patent number: 6181210Abstract: A high precision charge pump used in a phase-lock-loop incorporating a phase/frequency detector is designed and constructed to substantially eliminate the effects of DC offset and glitch errors on the charge pump output current. The high precision charge pump is constructed of parallel current paths each having a central node which is, in turn, connected to a feedback element. The feedback element defines a feedback current which is applied to the charge pump so as to maintain the two central nodes at an equi-potential level and to maintain the value of the pump-down current exactly equal to the value of the pump-up current output by the device.Type: GrantFiled: September 16, 1999Date of Patent: January 30, 2001Assignee: Broadcom CorporationInventor: Myles H. Wakayama
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Patent number: 5243235Abstract: A sample-and-hold circuit comprising a diode circuit including four diodes connected in series, an input circuit connected to a first node of the first and third diodes and a second node of the second and fourth diodes, first and second output terminals connected to a third node of the first and second diodes and a fourth node of the third and fourth diodes, two capacitors connected to the third and fourth nodes, respectively, and a current mirror circuit having a first terminal connected to the input circuit, a second terminal connected to the first node, and a third terminal connected to the second node, for supplying to the second and third terminals, a DC bias current and a dynamic current corresponding to the slew rate of the input signal flowing through the first terminal of the current mirror circuit.Type: GrantFiled: October 30, 1991Date of Patent: September 7, 1993Assignee: Kabushiki Kaisha ToshibaInventors: Myles H. Wakayama, Hiroshi Tanimoto
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Patent number: 5079518Abstract: A current-mirror circuit includes a pair of NMOS transistors. The first NMOS transistor has a gate electrode, a drain electrode serving as a current input terminal of the current-mirror circuit and a source electrode connected to a preselected potential. The second NMOS transistor has a gate electrode connected to the gate electrode of the first NMOS transistor, a drain electrode serving as a current output terminal of the current-mirror circuit and a source electrode connected to the preselected potential. The current-mirror circuit is provided with a buffer circuit. The buffer circuit includes a bipolar transistor which is opposite in polarity to the paired NMOS transistors, i.e., a PNP bipolar transistor. This transistor is associated with a constant current source.Type: GrantFiled: November 16, 1990Date of Patent: January 7, 1992Assignee: Kabushiki Kaisha ToshibaInventor: Myles H. Wakayama