Abstract: A method and system for displaying information on an electronic paper (or “e-paper”) is included herein. The method includes passing the e-paper through an e-paper printer. Additionally, the method includes changing a status of a pixel on the e-paper.

Abstract: A system and method of adding a new printer function to a printer is disclosed herein. The system includes the printer. The system also includes a general purpose computing device communicatively coupled to the printer.

Abstract: A method and system for displaying information on an electronic paper (or “e-paper”) is included herein. The method includes passing the e-paper through an e-paper printer. Additionally, the method includes changing a status of a pixel on the e-paper.

Abstract: A method and system for printing information from a remote source is describes herein. The system includes a printer configured to directly access an information source, obtain information from the information source, and print the information.

Abstract: Providing flow control includes receiving at a router an indication of the ability of each one of multiple ports not directly connected to the router to receive data from the router and controlling transmission of data from the router to the multiple ports based at least on the indication.

Abstract: The invention features a method for transferring data to programming engines using multiple memory channels, parsing data over at most two channels in the memory channels, and establishing at most two logical states to signal completion of a memory transfer operation.

Abstract: A graphical user interface (GUI) includes state indicators which show states of execution of threads running in microengines of a processor. The state indicators show the states of execution as functions of clocking in the processor. The GUI also includes a window showing computer code corresponding to one of the threads.

Abstract: A system and method for employing multiple hardware contexts and programming engines in a functional pipeline partitioned to facilitate high performance data processing. The system and method includes processing a sequence of packets with a sequence of threads, with the sequence of threads spanning multiple programmable processing elements integrated within a processor, and with the programmable processing elements providing multiple threads of execution such that each of the threads acquires exclusive modification access to data shared.

Abstract: A mechanism to process units of data associated with a dependent data stream using different threads of execution and a common data structure in memory. Accessing the common data structure in memory for the processing uses a single read operation and a single write operation. The folding of multiple read-modify-write memory operations in such a manner for multiple multi-threaded stages of processing includes controlling a first stage, which operates on the same data unit as a second stage to pass context state information to the second stage for coherency.

Abstract: A bus mechanism to control information exchanges between bus masters and bus targets over a bus structure that includes separate command, push and pull data buses. Commands are generated by bus masters and are interpreted by bus targets on a per-target basis. Each bus target controls the servicing of a command intended for such target by controlling the transfer of push data over the push bus to a bus master specified in the command as a destination, for a push operation type, and by controlling the transfer of pull data over the pull bus to the target from a bus master specified in the command as a destination, for a pull operation type. Arbitration logic associated with each bus is used to control the flow of the information exchanges on that bus.

Abstract: A system and method for employing multiple hardware contexts and programming engines in a functional pipeline partitioned to facilitate high performance data processing. The system and method includes a parallel processor that assigns system functions for processing data including programming engines that support multiple contexts arranged to provide a functional pipeline by a functional pipeline control unit that passes functional data among the programming engines.

Abstract: A graphical user interface (GUI) includes state indicators which show states of execution of threads running in microengines of a processor. The state indicators show the states of execution as functions of clocking in the processor. The GUI also includes a window showing computer code corresponding to one of the threads.

Abstract: Providing flow control includes receiving at a router an indication of the ability of each one of multiple ports not directly connected to the router to receive data from the router and controlling transmission of data from the router to the multiple ports based at least on the indication.

Abstract: The invention features a method for transferring data to programming engines using multiple memory channels, parsing data over at most two channels in the memory channels, and establishing at most two logical states to signal completion of a memory transfer operation.

Abstract: A graphical user interface (GUI) includes state indicators which show states of execution of threads running in microengines of a processor. The state indicators show the states of execution as functions of clocking in the processor. The GUI also includes a window showing computer code corresponding to one of the threads.

Abstract: A system and method for employing multiple hardware contexts and programming engines in a functional pipeline partitioned to facilitate high performance data processing. The system and method includes a parallel processor that assigns system functions for processing data including programming engines that support multiple contexts arranged to provide a functional pipeline by a functional pipeline control unit that passes functional data among the programming engines.

Abstract: A bus mechanism to control information exchanges between bus masters and bus targets over a bus structure that includes separate command, push and pull data buses. Commands are generated by bus masters and are interpreted by bus targets on a per-target basis. Each bus target controls the servicing of a command intended for such target by controlling the transfer of push data over the push bus to a bus master specified in the command as a destination, for a push operation type, and by controlling the transfer of pull data over the pull bus to the target from a bus master specified in the command as a destination, for a pull operation type. Arbitration logic associated with each bus is used to control the flow of the information exchanges on that bus.