Patents by Inventor Myoung-Gon Kang
Myoung-Gon Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8446766Abstract: A nonvolatile memory device comprises a memory cell array comprising a plurality of memory blocks each divided into a plurality of regions, and a control logic component. The control logic component selects a memory block to be programmed based on program/erase cycles of the memory blocks, and selects a program rule used to program the regions of the selected memory block.Type: GrantFiled: September 27, 2012Date of Patent: May 21, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Ki Tae Park, Myoung Gon Kang
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Patent number: 8300463Abstract: A nonvolatile memory device comprises a memory cell array comprising a plurality of memory blocks each divided into a plurality of regions, and a control logic component. The control logic component selects a memory block to be programmed based on program/erase cycles of the memory blocks, and selects a program rule used to program the regions of the selected memory block.Type: GrantFiled: March 18, 2010Date of Patent: October 30, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Ki Tae Park, Myoung Gon Kang
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Patent number: 8154924Abstract: Disclosed is a nonvolatile memory including a memory cell array including a first cell string connected between a first bit line and a first common source line, and a second cell string a second common source line and a second bit line adjacent to the first bit line. The nonvolatile memory also includes a control logic circuit configured to independently control the first and second common source lines.Type: GrantFiled: July 21, 2009Date of Patent: April 10, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Kitae Park, Myoung Gon Kang
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Patent number: 8144517Abstract: A method and device for adaptive control of multilayered nonvolatile semiconductor memory are provided, the device including memory cells organized into groups and a control circuit having a look-up matrix for providing control parameters for each of the groups, where characteristics of each group are stored in the look-up matrix, and the control parameters for each group are responsive to the stored characteristics for that group; the method including organizing memory cells into groups, storing characteristics for each group in a look-up matrix, providing control parameters for each of the groups, where the control parameters for each group are responsive to its stored characteristics, and driving each memory cell in accordance with its provided control parameters.Type: GrantFiled: May 26, 2009Date of Patent: March 27, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Doo Gon Kim, Ki Tae Park, Myoung Gon Kang
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Patent number: 8089811Abstract: Flash memory devices include a first memory cell string including a plurality of serially-connected memory cells and first and second serially-connected dummy transistors configured to couple the serially-connected memory cells to a bit line and a second memory cell string including a plurality of serially-connected memory cells and first and second serially-connected dummy transistors configured to couple the serially-connected memory cells to the bit line. The first dummy memory cells of the first and second memory cell strings have gates connected in common to a first dummy word line and have different threshold voltages and the second dummy memory cells of the first and second memory cell strings have gates connected in common to a second dummy bit line and have different threshold voltages.Type: GrantFiled: October 16, 2009Date of Patent: January 3, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Myoung Gon Kang, Kitae Park
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Patent number: 7940578Abstract: A flash memory device includes first and second memory cell array blocks and a row decoder coupled to the first memory cell array block and the second memory cell array block. The row decoder includes a block decoder, a single high voltage level shifter that is coupled to both the first and second memory cell array blocks, the single high voltage level shifter configured to provide a block wordline signal of a high voltage to the first and second memory array blocks in response to a block selection signal received from the block decoder, a first pass transistor unit, and a second pass transistor unit.Type: GrantFiled: January 14, 2009Date of Patent: May 10, 2011Assignee: Samsung Electronics Co., ltd.Inventors: Myoung-gon Kang, Yeong-taek Lee, Ki-tae Park, Doo-gon Kim
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Patent number: 7933154Abstract: A non-volatile memory device includes a memory cell array from which data is read via a plurality of bitlines, which includes a plurality of memory cells having gates respectively connected with a plurality of wordlines, a first type global wordline decoder configured to selectively apply n different voltages, where n is an integer greater than or equal to 3, to a corresponding wordline of the plurality of wordlines in a program mode, and a second type global wordline decoder configured to selectively apply (n?1) different voltages to a corresponding wordline of the plurality of wordlines in the program mode, the second type global wordline decoder having fewer switching elements than the first type global wordline decoder.Type: GrantFiled: June 26, 2008Date of Patent: April 26, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Myoung Gon Kang, Ki Tae Park, Doo Gon Kim, Yeong Taek Lee
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Publication number: 20100246266Abstract: A nonvolatile memory device comprises a memory cell array comprising a plurality of memory blocks each divided into a plurality of regions, and a control logic component. The control logic component selects a memory block to be programmed based on program/erase cycles of the memory blocks, and selects a program rule used to program the regions of the selected memory block.Type: ApplicationFiled: March 18, 2010Publication date: September 30, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ki Tae PARK, Myoung Gon KANG
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Patent number: 7777999Abstract: An electrostatic discharge (ESD) protection device includes an I/O terminal structure and a current discharge structure. The current discharge structure includes a conductive region separated from a bridge region by a gate electrode, a well region formed below the conductive region, another well region separated from the well region by another conductive region, and multiple additional conductive regions implementing dual current discharge paths through another well region.Type: GrantFiled: January 7, 2008Date of Patent: August 17, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Myoung-Gon Kang, Ki-Whan Song
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Publication number: 20100097862Abstract: Flash memory devices include a first memory cell string including a plurality of serially-connected memory cells and first and second serially-connected dummy transistors configured to couple the serially-connected memory cells to a bit line and a second memory cell string including a plurality of serially-connected memory cells and first and second serially-connected dummy transistors configured to couple the serially-connected memory cells to the bit line. The first dummy memory cells of the first and second memory cell strings have gates connected in common to a first dummy word line and have different threshold voltages and the second dummy memory cells of the first and second memory cell strings have gates connected in common to a second dummy bit line and have different threshold voltages.Type: ApplicationFiled: October 16, 2009Publication date: April 22, 2010Inventors: Myoung Gon Kang, Kitae Park
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Publication number: 20100046290Abstract: A flash memory device includes a first switch connecting one of a first cell string and a second cell string to a first bit line selectively, a second switch connecting the second cell string to a second bit line, and a control logic circuit providing bias voltages to the first and second cell strings through the first and second bit lines respectively and controlling the first and second cell stings to be simultaneously programmed.Type: ApplicationFiled: July 27, 2009Publication date: February 25, 2010Applicant: Samsung Electronics Co., Ltd.Inventors: Ki-Tae PARK, Myoung Gon KANG
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Publication number: 20100039861Abstract: Disclosed is a nonvolatile memory including a memory cell array including a first cell string connected between a first bit line and a first common source line, and a second cell string a second common source line and a second bit line adjacent to the first bit line. The nonvolatile memory also includes a control logic circuit configured to independently control the first and second common source lines.Type: ApplicationFiled: July 21, 2009Publication date: February 18, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kitae Park, Myoung Gon Kang
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Publication number: 20090273977Abstract: A method and device for adaptive control of multilayered nonvolatile semiconductor memory are provided, the device including memory cells organized into groups and a control circuit having a look-up matrix for providing control parameters for each of the groups, where characteristics of each group are stored in the look-up matrix, and the control parameters for each group are responsive to the stored characteristics for that group; the method including organizing memory cells into groups, storing characteristics for each group in a look-up matrix, providing control parameters for each of the groups, where the control parameters for each group are responsive to its stored characteristics, and driving each memory cell in accordance with its provided control parameters.Type: ApplicationFiled: May 26, 2009Publication date: November 5, 2009Inventors: Doo Gon Kim, Ki Tae Park, Myoung Gon Kang
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Publication number: 20090185422Abstract: A flash memory device includes first and second memory cell array blocks and a row decoder coupled to the first memory cell array block and the second. memory cell array block. The row decoder includes a block decoder, a single high voltage level shifter that is coupled to both the first and second memory cell array blocks, the single high voltage level shifter configured to provide a block wordline signal of a high voltage to the first and second memory array blocks in response to a block selection signal received from the block decoder, a first pass transistor unit, and a second pass transistor unit.Type: ApplicationFiled: January 14, 2009Publication date: July 23, 2009Inventors: Myoung-gon Kang, Yeong-taek Lee, Ki-tae Park, Doo-gon Kim
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Patent number: 7539041Abstract: A semiconductor memory device includes a memory cell array having first and second blocks, respectively including first and second memory cells with floating bodies. The first memory cell is connected between a first bit line and a source line, and the second memory cell is connected between a second bit line and the source line. A sense amplifier equalizes the sense bit line and the inverted sense bit line to be an equalization voltage during an equalization operation, pre-charges the sense bit line and the inverted sense bit line to first and second pre-charge voltages during a pre-charge operation, and amplifies a voltage difference between the sense bit line and the inverted sense bit line during read and write operations. The first pre-charge voltage is higher than the equalization voltage and the second pre-charge voltage is higher than the equalization voltage and lower than the first pre-charge voltage.Type: GrantFiled: July 23, 2007Date of Patent: May 26, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Doo-Gon Kim, Duk-Ha Park, Myoung-Gon Kang
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Publication number: 20090003067Abstract: A non-volatile memory device includes a memory cell array from which data is read via a plurality of bitlines, which includes a plurality of memory cells having gates respectively connected with a plurality of wordlines, a first type global wordline decoder configured to selectively apply n different voltages, where n is an integer greater than or equal to 3, to a corresponding wordline of the plurality of wordlines in a program mode, and a second type global wordline decoder configured to selectively apply (n?1) different voltages to a corresponding wordline of the plurality of wordlines in the program mode, the second type global wordline decoder having fewer switching elements than the first type global wordline decoder.Type: ApplicationFiled: June 26, 2008Publication date: January 1, 2009Inventors: Myoung Gon Kang, Ki Tae Park, Dao Gon Kim, Yeong Taek Lee
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Publication number: 20080174924Abstract: An electrostatic discharge (ESD) protection device includes an I/O terminal structure and a current discharge structure. The current discharge structure includes a conductive region separated from a bridge region by a gate electrode, a well region formed below the conductive region, another well region separated from the well region by another conductive region, and multiple additional conductive regions implementing dual current discharge paths through another well region.Type: ApplicationFiled: January 7, 2008Publication date: July 24, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Myoung-Gon KANG, Ki-Whan SONG
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Publication number: 20080101114Abstract: A semiconductor memory device includes a memory cell array having first and second blocks, respectively including first and second memory cells with floating bodies. The first memory cell is connected between a first bit line and a source line, and the second memory cell is connected between a second bit line and the source line. A sense amplifier equalizes the sense bit line and the inverted sense bit line to be an equalization voltage during an equalization operation, pre-charges the sense bit line and the inverted sense bit line to first and second pre-charge voltages during a pre-charge operation, and amplifies a voltage difference between the sense bit line and the inverted sense bit line during read and write operations. The first pre-charge voltage is higher than the equalization voltage and the second pre-charge voltage is higher than the equalization voltage and lower than the first pre-charge voltage.Type: ApplicationFiled: July 23, 2007Publication date: May 1, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Doo-Gon KIM, Duk-Ha PARK, Myoung-Gon KANG