Abstract: A multi-finger type electrostatic discharge protection circuit is disclosed, In an NMOS type ESD protection circuit, a pair of gates are formed in parallel with each other in one of multiple active regions so as to enable all the gate fingers in the active regions to perform npn bipolar operations uniformly. The present invention discharges an ESD pulse effectively by forming one or more additional n+ (or p+) type active regions, which are connected to Vcc (or Vss), between respective active regions.

Abstract: An ESD protection circuit including an NMOS transistor connected between an input/output pad and a ground. The NMOS transistor has a parasitic bipolar transistor, and at least one diode is connected between the input/output pad and the NMOS transistor.

Abstract: A method for fabricating a semiconductor device and an isolation structure thereof is disclosed. The isolation structure of a semiconductor device includes a first isolation step for forming a line-shaped active region on a semiconductor substrate wherein the line-shaped active region is consecutive in a lengthy direction, and a second isolation step for electrically isolating the line-shaped active regions in a lengthy direction by a predetermined length for thereby overcoming the problems such as a rounded corner portion problem, a pattern length decrease, etc. and enhancing the integrity of the semiconductor device.

Abstract: An ESD (Electro-Static Discharge) protection circuit includes a semiconductor substrate having an active region and field regions, isolating films formed in the field regions, a gate insulating film formed on the active region, and a gate electrode formed on the gate insulating film, first and second heavily doped impurity regions formed in a surface of the semiconductor substrate at sides of the gate electrode, a plurality of dummy gate electrodes formed on the second heavily doped impurity region and offset from the gate electrode, insulating sidewalls formed at the sides of the gate electrode and at sides of each of the dummy gate electrodes, and salicide films formed on a surface of the gate electrode, on surfaces of each of the dummy gate electrodes and on a surface of the first heavily doped impurity region.