Abstract: The present invention for increasing the sensing speed of the input/output line by preventing the potential difference between the bit line pair from being decreased when the bit line is connected to input/output line in a DRAM. A semiconductor memory device has a column gate connected between a bit line pair and an input/output line pair. A sense amplifier with a discharging node is connected to the bit line pair, and a pull down transistor has an electrode for controlling a current flow path which is disposed between the discharging node and a ground voltage node. A PMOS transistor has a channel between the charging node and an output node connected to the control electrode of the pull down transistor, and has a gate connected to a given first signal. A NMOS transistor has a channel between the output node and the ground voltage node, and has a gate connected to the first signal.