Abstract: A method of fabricating a semiconductor device is provided. The method includes: loading a substrate into a substrate processing apparatus; and processing the substrate, using the substrate processing apparatus. The processing the substrate includes: providing a process gas; generating a process etchant from the process gas, using plasma ignition, the process etchant including a first etchant and a second etchant; processing the substrate, using the process etchant; identifying a composition rate of the process etchant; and controlling the processing of the substrate based on a process result according to the composition rate of the process etchant.

Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate including a first region, a second region, and a connecting region placed between the first region and the second region, a plurality of first multi-channel active patterns placed in the first region of the substrate, a plurality of second multi-channel active patterns placed in the second region of the substrate, a first connecting fin type pattern which is placed in the connecting region of the substrate and extends from the first region to the second region in a first direction, and a field insulating film which is placed on the substrate and covers an upper surface of the first connecting fin type pattern, wherein a width of the first connecting fin type pattern in a second direction decreases and then increases as it goes away from the first region, and the first direction is perpendicular to the second direction.

Abstract: In one embodiment, the standard cell includes first and second active regions defining an intermediate region between the first and second active regions; and first, second and third gate lines crossing the first and second active regions and crossing the intermediate region. The first gate line is divided into an upper first gate line and a lower first gate line by a first gap insulating layer in the intermediate region, the second gate line is undivided, and the third gate line is divided into an upper third gate line and a lower third gate line by a second gap insulating layer in the intermediate region.

Abstract: A method of fabricating a semiconductor device includes: (i) placing, on a first layout, first patterns that extend parallel to each other in a first direction and are spaced apart from each other in a second direction intersecting the first direction, (ii) extracting a low-density region on the first layout, (iii) defining an enclosure region that surrounds the first patterns, (iv) placing dot patterns on a second layout, (v) extracting, from the dot patterns, first dot patterns that overlap the low-density region and do not overlap the enclosure region, (vi) placing the extracted first dot patterns on the first layout, (vii) allowing the first dot patterns to extend in the first direction to form second patterns, and (viii) using the first and second patterns to respectively form first and second active patterns on a substrate.

Abstract: A method of fabricating a semiconductor device includes: (i) placing, on a first layout, first patterns that extend parallel to each other in a first direction and are spaced apart from each other in a second direction intersecting the first direction, (ii) extracting a low-density region on the first layout, (iii) defining an enclosure region that surrounds the first patterns, (iv) placing dot patterns on a second layout, (v) extracting, from the dot patterns, first dot patterns that overlap the low-density region and do not overlap the enclosure region, (vi) placing the extracted first dot patterns on the first layout, (vii) allowing the first dot patterns to extend in the first direction to form second patterns, and (viii) using the first and second patterns to respectively form first and second active patterns on a substrate.

Abstract: A semiconductor device comprises a first fin-type pattern comprising a first long side extending in a first direction, and a first short side extending in a second direction. A second fin-type pattern is arranged substantially parallel to the first fin-type pattern. A first gate electrode intersects the first fin-type pattern and the second fin-type pattern. The second fin-type pattern comprises a protrusion portion that protrudes beyond the first short side of the first fin-type pattern. The first gate electrode overlaps with an end portion of the first fin-type pattern that comprises the first short side of the first fin-type pattern. At least part of a first sidewall of the first fin-type pattern that defines the first short side of the first fin-type pattern is defined by a first trench having a first depth. The first trench directly adjoins a second trench having a second, greater, depth.

Abstract: A method of manufacturing a semiconductor device is provided as follows. A mask layout for forming a target pattern of a multi-height cell including a rectangular notch is generated. A preliminary rectangular mask pattern corresponding to the rectangular notch is detected from the mask layout. The multi-height cell is formed of standard cells arranged and connected to each other in a direction and the rectangular notch is disposed between two adjacent standard cells. A hexagonal mask pattern is, in response to the detecting of the preliminary rectangular mask pattern, placed on at least one short side of the preliminary rectangular mask pattern to generate a combined mask pattern. An outer boundary of the combined mask pattern remains in the mask layout and corresponds to the rectangular notch of the target pattern. A target mask and the semiconductor device are formed based on the combined mask pattern.

Abstract: In one embodiment, the standard cell includes first and second active regions defining an intermediate region between the first and second active regions; and first, second and third gate lines crossing the first and second active regions and crossing the intermediate region. The first gate line is divided into an upper first gate line and a lower first gate line by a first gap insulating layer in the intermediate region, the second gate line is undivided, and the third gate line is divided into an upper third gate line and a lower third gate line by a second gap insulating layer in the intermediate region.

Abstract: In one embodiment, the standard cell includes first and second active regions defining an intermediate region between the first and second active regions; and first, second and third gate lines crossing the first and second active regions and crossing the intermediate region. The first gate line is divided into an upper first gate line and a lower first gate line by a first gap insulating layer in the intermediate region, the second gate line is undivided, and the third gate line is divided into an upper third gate line and a lower third gate line by a second gap insulating layer in the intermediate region.

Abstract: A semiconductor device comprises a first fin-type pattern comprising a first long side extending in a first direction, and a first short side extending in a second direction. A second fin-type pattern is arranged substantially parallel to the first fin-type pattern. A first gate electrode intersects the first fin-type pattern and the second fin-type pattern. The second fin-type pattern comprises a protrusion portion that protrudes beyond the first short side of the first fin-type pattern. The first gate electrode overlaps with an end portion of the first fin-type pattern that comprises the first short side of the first fin-type pattern. At least part of a first sidewall of the first fin-type pattern that defines the first short side of the first fin-type pattern is defined by a first trench having a first depth. The first trench directly adjoins a second trench having a second, greater, depth.

Abstract: A method of manufacturing a semiconductor device is provided as follows. A mask layout for forming a target pattern of a multi-height cell including a rectangular notch is generated. A preliminary rectangular mask pattern corresponding to the rectangular notch is detected from the mask layout. The multi-height cell is formed of standard cells arranged and connected to each other in a direction and the rectangular notch is disposed between two adjacent standard cells. A hexagonal mask pattern is, in response to the detecting of the preliminary rectangular mask pattern, placed on at least one short side of the preliminary rectangular mask pattern to generate a combined mask pattern. An outer boundary of the combined mask pattern remains in the mask layout and corresponds to the rectangular notch of the target pattern. A target mask and the semiconductor device are formed based on the combined mask pattern.

Abstract: A semiconductor device comprises a first fin-type pattern comprising a first long side extending in a first direction, and a first short side extending in a second direction. A second fin-type pattern is arranged substantially parallel to the first fin-type pattern. A first gate electrode intersects the first fin-type pattern and the second fin-type pattern. The second fin-type pattern comprises a protrusion portion that protrudes beyond the first short side of the first fin-type pattern. The first gate electrode overlaps with an end portion of the first fin-type pattern that comprises the first short side of the first fin-type pattern. At least part of a first sidewall of the first fin-type pattern that defines the first short side of the first fin-type pattern is defined by a first trench having a first depth. The first trench directly adjoins a second trench having a second, greater, depth.

Abstract: In one embodiment, the standard cell includes first and second active regions defining an intermediate region between the first and second active regions; and first, second and third gate lines crossing the first and second active regions and crossing the intermediate region. The first gate line is divided into an upper first gate line and a lower first gate line by a first gap insulating layer in the intermediate region, the second gate line is undivided, and the third gate line is divided into an upper third gate line and a lower third gate line by a second gap insulating layer in the intermediate region.

Abstract: A semiconductor device comprises a first fin-type pattern comprising a first long side extending in a first direction, and a first short side extending in a second direction. A second fin-type pattern is arranged substantially parallel to the first fin-type pattern. A first gate electrode intersects the first fin-type pattern and the second fin-type pattern. The second fin-type pattern comprises a protrusion portion that protrudes beyond the first short side of the first fin-type pattern. The first gate electrode overlaps with an end portion of the first fin-type pattern that comprises the first short side of the first fin-type pattern. At least part of a first sidewall of the first fin-type pattern that defines the first short side of the first fin-type pattern is defined by a first trench having a first depth. The first trench directly adjoins a second trench having a second, greater, depth.

Abstract: In one embodiment, the standard cell includes first and second active regions defining an intermediate region between the first and second active regions; and first, second and third gate lines crossing the first and second active regions and crossing the intermediate region. The first gate line is divided into an upper first gate line and a lower first gate line by a first gap insulating layer in the intermediate region, the second gate line is undivided, and the third gate line is divided into an upper third gate line and a lower third gate line by a second gap insulating layer in the intermediate region.

Abstract: A semiconductor device comprises a first fin-type pattern comprising a first long side extending in a first direction, and a first short side extending in a second direction. A second fin-type pattern is arranged substantially parallel to the first fin-type pattern. A first gate electrode intersects the first fin-type pattern and the second fin-type pattern. The second fin-type pattern comprises a protrusion portion that protrudes beyond the first short side of the first fin-type pattern. The first gate electrode overlaps with an end portion of the first fin-type pattern that comprises the first short side of the first fin-type pattern. At least part of a first sidewall of the first fin-type pattern that defines the first short side of the first fin-type pattern is defined by a first trench having a first depth. The first trench directly adjoins a second trench having a second, greater, depth.

Abstract: A semiconductor device includes a substrate that includes active patterns extending in a second direction, a third device isolation layer disposed on an upper portion of the substrate that includes a PMOSFET region and an NMOSFET region, and a gate electrode that extends across the active patterns in a first direction that crosses the second direction. The active patterns extend across the PMOSFET region and the NMOSFET region. The third device isolation layer lies between the PMOSFET region and the NMOSFET region. The third device isolation layer comprises a first part that extends in the second direction and a second part that extends in a third direction that crosses the first and second directions. The second part has opposite sidewalls parallel to the third direction, in a plan view.

Abstract: A semiconductor device comprises a first fin-type pattern comprising a first long side extending in a first direction, and a first short side extending in a second direction. A second fin-type pattern is arranged substantially parallel to the first fin-type pattern. A first gate electrode intersects the first fin-type pattern and the second fin-type pattern. The second fin-type pattern comprises a protrusion portion that protrudes beyond the first short side of the first fin-type pattern. The first gate electrode overlaps with an end portion of the first fin-type pattern that comprises the first short side of the first fin-type pattern. At least part of a first sidewall of the first fin-type pattern that defines the first short side of the first fin-type pattern is defined by a first trench having a first depth. The first trench directly adjoins a second trench having a second, greater, depth.

Abstract: A semiconductor device includes a substrate that includes active patterns extending in a second direction, a third device isolation layer disposed on an upper portion of the substrate that includes a PMOSFET region and an NMOSFET region, and a gate electrode that extends across the active patterns in a first direction that crosses the second direction. The active patterns extend across the PMOSFET region and the NMOSFET region. The third device isolation layer lies between the PMOSFET region and the NMOSFET region. The third device isolation layer comprises a first part that extends in the second direction and a second part that extends in a third direction that crosses the first and second directions. The second part has opposite sidewalls parallel to the third direction, in a plan view.

Abstract: In one embodiment, the standard cell includes first and second active regions defining an intermediate region between the first and second active regions; and first, second and third gate lines crossing the first and second active regions and crossing the intermediate region. The first gate line is divided into an upper first gate line and a lower first gate line by a first gap insulating layer in the intermediate region, the second gate line is undivided, and the third gate line is divided into an upper third gate line and a lower third gate line by a second gap insulating layer in the intermediate region.