Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a memory cell string including a plurality of memory cells coupled to a plurality of word lines, a peripheral circuit configured to perform an operation that applies an operating voltage to a selected word line and applying a pass voltage to unselected word lines, among the plurality of word lines, and an operation controller configured to control the peripheral circuit to perform, after the operation has been performed, a discharge operation that sequentially decreases voltages of the plurality of word lines that range from at least one central word line located in a central portion in relation to the memory cell string to a word line, among the plurality of word lines, located in an outermost portion in relation to the memory cell string, adjacent to a select line.

Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a substrate with a complementary metal oxide semiconductor (CMOS) circuit; a gate stacked body with interlayer insulating layers and conductive patterns that are alternately stacked on the substrate in a vertical direction; a plurality of channel structures passing through the gate stacked body, each with a first end that protrudes above the gate stacked body; and a plurality of conductive layers disposed over the gate stacked body. Each of the plurality of conductive layers is in contact with the first end of at least one of the plurality of channel structures.

Abstract: A semiconductor memory device includes a memory cell array and a control logic. The memory cell array includes a plurality of memory blocks. The control logic groups the memory blocks, determines driving voltages to be respectively applied to the groups, and applies each of the determined driving voltages to memory blocks included in a corresponding group to control the operation of the memory cell array.

Abstract: A semiconductor memory device may include a control logic. The control logic may be coupled to bit lines through a read and write (read/write) circuit and to word lines. The control logic is configured to determine a duration of an activation time of a strobe signal for the read/write circuit.

Abstract: A semiconductor memory device may include a control logic. The control logic may be coupled to bit lines through a read and write (read/write) circuit and to word lines. The control logic is configured to determine a duration of an activation time of a strobe signal for the read/write circuit.

Abstract: Provided herein is a semiconductor memory device and an operating method thereof. The semiconductor memory device includes a memory cell array and a control logic. The memory cell array includes a plurality of memory blocks. The control logic groups the memory blocks, determines driving voltages to be respectively applied to the groups, and applies each of the determined driving voltages to memory blocks included in a corresponding group to control the operation of the memory cell array.

Abstract: A NAND-type non-volatile memory device includes a substrate and a device isolation layer disposed on the substrate to define an active region. First and second selection transistors are disposed in the active region, such that each of the first and second selection transistors has a recessed channel. A plurality of memory transistors is disposed in the active region between the first selection transistor and the second selection transistor.

Abstract: Integrated circuit devices are provided including an integrated circuit substrate and first, second and third spaced apart insulating regions in the integrated circuit substrate that define first and second active regions. A first gate electrode is provided on the first active region. The first gate electrode has a first portion on the first active region that extends onto the first insulating region and a second portion at an end of the first portion on the first insulating region. A second gate electrode is provided on the second active region. An insulating layer is provided on the first, second and third active regions defining a first gate contact hole that exposes at least a portion of the second portion of the first gate electrode. The first gate electrode is free of a gate contact hole on the first portion of the first gate electrode. A second gate contact hole is provided on the second active region that exposes at least a portion of the second gate electrode.

Abstract: Unit cells of silicon-oxide-nitride-oxide-silicon (SONOS) memory devices are provided. The unit cells include an integrated circuit substrate and a SONOS memory cell on the integrated circuit substrate. The SONOS memory cell includes a source region, a drain region and a gate contact. The integrated circuit substrate defines a trench between the source and drain regions and the gate contact is provided in the trench. A floor of the trench extends further into the integrated circuit substrate than lower surfaces of the source and drain regions. Related methods of fabricating SONOS memory cells are also provided.

Abstract: Integrated circuit devices are provided including an integrated circuit substrate and first, second and third spaced apart insulating regions in the integrated circuit substrate that define first and second active regions. A first gate electrode is provided on the first active region. The first gate electrode has a first portion on the first active region that extends onto the first insulating region and a second portion at an end of the first portion on the first insulating region. A second gate electrode is provided on the second active region. An insulating layer is provided on the first, second and third active regions defining a first gate contact hole that exposes at least a portion of the second portion of the first gate electrode. The first gate electrode is free of a gate contact hole on the first portion of the first gate electrode. A second gate contact hole is provided on the second active region that exposes at least a portion of the second gate electrode.

Abstract: Integrated circuit devices are provided including an integrated circuit substrate and first, second and third spaced apart insulating regions in the integrated circuit substrate that define first and second active regions. A first gate electrode is provided on the first active region. The first gate electrode has a first portion on the first active region that extends onto the first insulating region and a second portion at an end of the first portion on the first insulating region. A second gate electrode is provided on the second active region. An insulating layer is provided on the first, second and third active regions defining a first gate contact hole that exposes at least a portion of the second portion of the first gate electrode. The first gate electrode is free of a gate contact hole on the first portion of the first gate electrode. A second gate contact hole is provided on the second active region that exposes at least a portion of the second gate electrode.

Abstract: A NAND-type non-volatile memory device includes a substrate and a device isolation layer disposed on the substrate to define an active region. First and second selection transistors are disposed in the active region, such that each of the first and second selection transistors has a recessed channel. A plurality of memory transistors is disposed in the active region between the first selection transistor and the second selection transistor.

Abstract: Unit cells of silicon-oxide-nitride-oxide-silicon (SONOS) memory devices are provided. The unit cells include an integrated circuit substrate and a SONOS memory cell on the integrated circuit substrate. The SONOS memory cell includes a source region, a drain region and a gate contact. The integrated circuit substrate defines a trench between the source and drain regions and the gate contact is provided in the trench. A floor of the trench extends further into the integrated circuit substrate than lower surfaces of the source and drain regions. Related methods of fabricating SONOS memory cells are also provided.

Abstract: Provided is a method for operating a NOR-type flash memory device using SONOS cells. The SONOS cells are selectively programmed using channel hot electron injection and erased using Fowler-Nordheim tunneling and hot hole injection. When the SONOS cells are programmed, a voltage within a range of 8V-12V is applied to a selected word line and a voltage within a range of 3V-6V is applied to a selected bit line. When the SONOS cells are erased, the selected word line is ground and a voltage within a range of 13V-18V is applied to a substrate. Alternatively, a voltage of about ?8V is applied to the selected word line, a voltage of about 6V is applied to the substrate, and a bit line and a source line float.

Abstract: Integrated circuit devices are provided including an integrated circuit substrate and first, second and third spaced apart insulating regions in the integrated circuit substrate that define first and second active regions. A first gate electrode is provided on the first active region. The first gate electrode has a first portion on the first active region that extends onto the first insulating region and a second portion at an end of the first portion on the first insulating region. A second gate electrode is provided on the second active region. An insulating layer is provided on the first, second and third active regions defining a first gate contact hole that exposes at least a portion of the second portion of the first gate electrode. The first gate electrode is free of a gate contact hole on the first portion of the first gate electrode. A second gate contact hole is provided on the second active region that exposes at least a portion of the second gate electrode.

Abstract: Provided is a method for operating a NOR-type flash memory device using SONOS cells. The SONOS cells are selectively programmed using channel hot electron injection and erased using Fowler-Nordheim tunneling and hot hole injection. When the SONOS cells are programmed, a voltage within a range of 8V-12V is applied to a selected word line and a voltage within a range of 3V-6V is applied to a selected bit line. When the SONOS cells are erased, the selected word line is ground and a voltage within a range of 13V-18V is applied to a substrate. Alternatively, a voltage of about −8V is applied to the selected word line, a voltage of about 6V is applied to the substrate, and a bit line and a source line float.

Abstract: A nonvolatile memory device which suppress a drain coupling by minimizing an overlap capacitance between a floating gate and a drain. The nonvolatile memory device includes a cell array region in which a plurality of memory cells are two-dimensionally arranged and a peripheral circuit region for driving the memory cells. The memory cells comprise a first conductivity type semiconductor substrate, second conductivity type source and drain regions separated from each other with a channel region therebetween on the main surface of the semiconductor substrate, a gate oxide film formed on the upper portion of the channel region, a floating gate formed on the gate oxide film, an interlayer dielectric film formed on the upper portion of the floating gate, a control gate formed on the interlayer dielectric film, and a bird's beak area formed between the source/drain regions and the floating gate having greater thickness than the gate oxide film.

Abstract: A nonvolatile memory device which suppress a drain coupling by minimizing an overlap capacitance between a floating gate and a drain. The nonvolatile memory device includes a cell array region in which a plurality of memory cells are two-dimensionally arranged and a peripheral circuit region for driving the memory cells. The memory cells comprise a first conductivity type semiconductor substrate, second conductivity type source and drain regions separated from each other with a channel region therebetween on the main surface of the semiconductor substrate, a gate oxide film formed on the upper portion of the channel region, a floating gate formed on the gate oxide film, an interlayer dielectric film formed on the upper portion of the floating gate, a control gate formed on the interlayer dielectric film, and a bird's beak area formed between the source/drain regions and the floating gate having greater thickness than the gate oxide film.

Abstract: Methods of forming EEPROM memory cells having uniformly thick tunneling oxide layers include the steps of forming a preliminary field oxide isolation region of first thickness at a face of a semiconductor substrate of first conductivity type (e.g., P-type) and then forming a tunneling oxide layer on the face, adjacent the preliminary field oxide isolation region. The memory cell's drain region dopants are then implanted through the preliminary field oxide isolation region and into the substrate to form a preliminary drain region of second conductivity type. The preliminary field oxide isolation region is then grown to a second thickness greater than the first thickness by oxidizing the portion of the substrate containing the implanted dopants, to form a final field oxide isolation region which may have a thickness of about 2000 .ANG..

Abstract: Flash EEPROM memory devices having mid-channel injection characteristics include a substrate having source and drain regions of first conductivity type therein extending adjacent a surface thereof. A stacked-gate electrode is also provided on the surface, between the source and drain regions. To provide improved mid-channel injection characteristics during programming, a preferred semiconductor channel region is provided in the substrate at a location extending opposite the stacked-gate electrode. This channel region comprises a first "source-side" region of second conductivity type (e.g., P+) and a second "drain-side" region of predetermined conductivity type (e.g., P-, N-). The second region has a lower first conductivity type dopant concentration therein than the drain region and a lower second conductivity type dopant concentration therein than said first region, and more preferably has a lower second conductivity type dopant concentration therein than said substrate.