Abstract: Provided are semiconductor devices including device isolation layers. The semiconductor device includes a substrate having a cell region and a core/peripheral region, a first active region in the cell region of the substrate, a first device isolation layer that defines the first active region, a second active region in the core/peripheral region of the substrate; and a second device isolation layer that defines the second active region. A height from a lower surface of the substrate to an upper end of the first device isolation layer in a first direction that is perpendicular to the lower surface of the substrate is less than or equal to a height from the lower surface of the substrate to an upper end of the first active region in the first direction.

Abstract: A semiconductor integrated circuit device and method of manufacturing the same is presented. The device comprises a first conductive line formed on a semiconductor substrate. An insulating layer formed on the first conductive line and the semiconductor substrate has a first contact hole exposing the first conductive line. A second conductive line consisting of a polysilicon layer and a silicide layer thereon is formed on the insulating layer including the first contact hole. The polysilicon layer of the second conductive line extends from the sidewall of the first contact hole to the top of the insulating layer so as to expose the first conductive line. The silicide layer of the second conductive line is directly connected to the exposed first conductive line in the first contact hole. Contact resistance between a bit line and a word line on the device can be reduced by directly contacting a silicide layer of the word line and a silicide layer of the bit line.

Abstract: A storage electrode structure and method of manufacturing thereof. Storage electrodes of dummy cells arranged in a word line direction and a bit line direction at the peripheral regions of a cell are formed such that every two or three dummy cells in a word line direction are formed in a single pattern. As a result, the loading effect produced in the peripheral regions of the cell region is reduced. The invention also reduces short-circuit bridging caused by collapsing storage electrode patterns in the dummy cells since the storage electrodes are not connected together. Accordingly, it is possible to minimize an increase in the loading capacitance of bit lines when an electrical short circuit occurs between a bit line and an associated buried contact.

Abstract: A method for forming an opening in an integrated circuit device with an improved aspect ratio includes the following steps. An inter-insulating layer is formed on a surface of a substrate. A recess having a first width is then formed in the inter-insulating layer. Next, a hole having a second width is formed in the inter-insulating layer at a base of the recess, wherein the first width is greater than the second width. Thus, an opening is formed to have a cross-sectional shape of a step where its upper portion formed by the recess which is wider than its lower portion formed by the hole. Accordingly, open circuits caused by voids formed in the opening in subsequent metal deposition steps may be prevented.

Abstract: Isolated semiconductor devices are formed by forming field oxide regions in a face of a semiconductor substrate to define active regions therebetween. The field oxide regions extend to above the substrate face and include an oblique surface which extends from above the substrate face to the substrate face. A step reducing region is formed on a respective one of the oblique surfaces of the field oxide regions, extending onto the active regions at the substrate face. The step reducing region can reduce the steepness of the step between the substrate face and the field oxide regions, thereby facilitating further processing and reliability of the semiconductor devices.

Abstract: Methods of forming field oxide isolation regions having sloped edges which facilitate uniform step coverage of subsequently patterned metallization, etc. but do not encroach upon semiconductor active regions, include the steps of patterning a first mask on a face of a semiconductor substrate to define an active region thereunder and then forming a pad insulation layer on the face of the substrate and in abutting relation to edges of the first mask. Oxidation resistant spacers are then formed on the edges of the first mask and on the pad insulation layer so that field oxide isolation regions having sloped edges can be formed by growing the pad insulation layer through oxidation so that it extends away from the edges of the first mask and does not undercut the first mask to form parasitic bird's beak oxide extensions.