Abstract: A method of forming a gate electrode, capable of minimizing a resistance difference between the gate electrodes and a method of forming a non-volatile memory device using the same, wherein an oxide film pattern, a polysilicon layer pattern and a hard mask pattern are stacked on a semiconductor substrate to form a gate structure; a gate spacer including an oxide-based insulating material is formed on a sidewall of the gate structure; the hard mask pattern stacked on the gate structure is removed to expose the polysilicon layer pattern; the polysilicon layer pattern and the top portion of the gate spacer are planarized; a stopping layer and an insulating interlayer are then formed and planarized by CMP. Thus, the thickness of the films for forming the gate electrode and, consequently the gate electrode resistance of a semiconductor device, are uniform across the wafer.

Abstract: A semiconductor device is formed by including the step of forming a polycrystalline silicon layer on a semiconductor substrate which includes a pad oxide. A trench is formed in the semiconductor substrate by etching sequentially a part of the polycrystalline silicon layer, a part of the pad oxide layer, and a part of the semiconductor substrate. An oxide layer spacer is formed on the walls of the trench and the side walls of the etched pad oxide layer and the etched polycrystalline silicon layer. A nitride liner is formed on the oxide layer spacer. The trench is filled with an insulating layer on the nitride liner and the insulating layer is planarized until the polycrystalline silicon layer is exposed. And then the polycrystalline silicon layer is dry-etched.

Abstract: A method of fabricating a semiconductor device having a capacitor with a high dielectric constant layer includes a groove for an alignment key is formed together with a contact hole on a substrate; a conductive layer of tungsten is formed to fill the contact hole and cover the inner surface of the groove; a capping layer for use as an oxygen barrier is stacked on the conductive layer of tungsten; a planarization process is performed using CMP to leave the capping layer and the conductive layer of tungsten covering the inner surface of the groove to form a contact plug filling the contact hole; a capacitor bottom electrode layer is stacked to contact the top surface of the contact plug; a high dielectric constant layer is stacked on the bottom electrode layer; and an oxidation treatment is performed at a high temperature to crystallize the high dielectric constant layer.

Abstract: A method of forming a gate electrode, capable of minimizing a resistance difference between the gate electrodes and a method of forming a non-volatile memory device using the same, wherein an oxide film pattern, a polysilicon layer pattern and a hard mask pattern are stacked on a semiconductor substrate to form a gate structure; a gate spacer including an oxide-based insulating material is formed on a sidewall of the gate structure; the hard mask pattern stacked on the gate structure is removed to expose the polysilicon layer pattern; the polysilicon layer pattern and the top portion of the gate spacer are planarized; a stopping layer and an insulating interlayer are then formed and planarized by CMP. Thus, the thickness of the films for forming the gate electrode and, consequently the gate electrode resistance of a semiconductor device, are uniform across the wafer.

Abstract: A method of fabricating a semiconductor device having a capacitor with a high dielectric constant layer includes a groove for an alignment key is formed together with a contact hole on a substrate; a conductive layer of tungsten is formed to fill the contact hole and cover the inner surface of the groove; a capping layer for use as an oxygen barrier is stacked on the conductive layer of tungsten; a planarization process is performed using CMP to leave the capping layer and the conductive layer of tungsten covering the inner surface of the groove to form a contact plug filling the contact hole; a capacitor bottom electrode layer is stacked to contact the top surface of the contact plug; a high dielectric constant layer is stacked on the bottom electrode layer; and an oxidation treatment is performed at a high temperature to crystallize the high dielectric constant layer.

Abstract: Disclosed is a polishing head of a chemical and mechanical polishing apparatus uniformly polishing a wafer. The polishing head has a body defining at least one air passage therein through which air is introduced into and exhausted from the polishing head. The body is movable upward and downward. An air pressure distributing member is mounted to a lower portion of the body for distributing a pressure of the air supplied through the air passage. A membrane is mounted to enclose a lower surface of the air pressure distributing member so as to be expanded and shrunk by the pressure of the air supplied through the air pressure distributing member. A surface of the air pressure distributing member makes contact with a back surface of a wafer. An air pressure compensating member makes uniformly the pressure that is applied to central and edge portions of the wafer which makes contact with the membrane.

Abstract: A semiconductor device is formed by including the step of forming a polycrystalline silicon layer on a semiconductor substrate which includes a pad oxide. A trench is formed in the semiconductor substrate by etching sequentially a part of the polycrystalline silicon layer, a part of the pad oxide layer, and a part of the semiconductor substrate. An oxide layer spacer is formed on the walls of the trench and the side walls of the etched pad oxide layer and the etched polycrystalline silicon layer. A nitride liner is formed on the oxide layer spacer. The trench is filled with an insulating layer on the nitride liner and the insulating layer is planarized until the polycrystalline silicon layer is exposed. And then the polycrystalline silicon layer is dry-etched.