Patents by Inventor Myoungsoo Jung
Myoungsoo Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12386657Abstract: A processor of the computing device includes a plurality of cores and executes one or more instructions stored in a memory module including a non-volatile memory, thereby performing a stop procedure upon a power failure and performing a go procedure upon power recovery. In the stop procedure, the processor accesses process control blocks of processes being run, scheduling each process to a run queue of a corresponding first core among first cores included in the cores, removes the scheduled process from the run queue and makes the removed process wait in a waiting queue, executes an idle task, and stops a device included in the computing device.Type: GrantFiled: March 18, 2022Date of Patent: August 12, 2025Assignees: MemRay Corporation, Korea Advanced Institute of Science and TechnologyInventors: Myoungsoo Jung, Miryeong Kwon, Gyuyoung Park, Sangwon Lee
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Publication number: 20250252049Abstract: A data storage device includes a memory array including a data region and a journal region; and a control circuit configured to generate journal region information including an address of the journal region, process a transaction command corresponding to a transaction based on the journal region information, and perform a checkpointing operation on a selected transaction among a predetermined number of transactions.Type: ApplicationFiled: January 31, 2025Publication date: August 7, 2025Inventors: Hanyeoreum BAE, Donghyun GOUK, Seungjun LEE, Jiseon KIM, Sungjoon KOH, Jie ZHANG, Myoungsoo JUNG
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Publication number: 20250231811Abstract: A method and an apparatus for classifying data and allocating blocks using the bit error rate. According to an embodiment of a present disclosure, a method for classifying data and allocating blocks using the bit error rate includes classifying data into first data and second data using information on quality of service (QoS) and a bit error rate. The method also includes determining a group ID using the information on QoS and a mapping table. The method also includes acquiring a block from an idle block pool of a group based on the group ID using the group ID. The method also includes allocating the block to the first data or the second data.Type: ApplicationFiled: October 29, 2024Publication date: July 17, 2025Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Myoungsoo JUNG, MinYoung CHOI, Miryeong KWON
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Patent number: 12294411Abstract: An electronic system for transmitting and receiving internal data through an optical channel. The electronic system may include a light emitter configured to generate a first optical signal, a first device configured to receive the first optical signal and including a transmitter configured to output a second optical signal representing a transmission value based on the first optical signal, a second device including a first receiver configured to receive the second optical signal from the first device and output a third optical signal by adjusting a light intensity of the second optical signal, and configured to read the transmission value based on the light intensity of the second optical signal, and a third device including a second receiver configured to receive the third optical signal from the second device, and configured to read the transmission value based on a light intensity of the third optical signal.Type: GrantFiled: May 22, 2023Date of Patent: May 6, 2025Assignees: SAMSUNG ELECTRONICS CO., LTD., KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Hanyeoreum Bae, Myoungsoo Jung, Jie Zhang
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Patent number: 12248814Abstract: Provided is an apparatus for accelerating graph neural network (GNN) pre-processing, the apparatus including a set-partitioning accelerator configured to sort each edge of an original graph stored in a coordinate list (COO) format by a node number, perform radix sorting based on a vertex identification (VID) to generate a COO array of a preset length, and perform uniform random sampling on some nodes of a given node array, a merger configured to merge the COO array of the preset length to generate one sorted COO array, a re-indexer configured to assign new consecutive VIDs respectively to the nodes selected through the uniform random sampling, and a compressed sparse row (CSR) converter configured to the edges sorted by the node number into a CSR format.Type: GrantFiled: August 22, 2023Date of Patent: March 11, 2025Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Myoungsoo Jung, Seungkwan Kang, Donghyun Gouk, Miryeong Kwon, Hyunkyu Choi, Junhyeok Jang
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Publication number: 20250061077Abstract: A memory expander is disclosed. The memory expander includes a memory, a memory controller configured to control the memory, a compute express link (CXL) engine configured to acquire a CXL flit from a host device connected to the memory expander and configured to acquire a calculation request for pieces of data stored in the memory by performing conversion on the CXL flit, and a domain-specific accelerator configured to perform a calculation in response to the calculation request.Type: ApplicationFiled: August 8, 2024Publication date: February 20, 2025Inventors: Myoungsoo JUNG, Miryeong Kwon, Junhyeok JANG, Seungjun LEE, Hanjin CHOI, Hanyeoreum BAE
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Publication number: 20250036572Abstract: A method and electronic circuit for memory replacement are provided. The method for memory replacement includes generating an input signal in response to an event for a memory, providing the input signal to a time-varying circuit including a plurality of time-varying devices, generating an output signal by reading a value stored in at least one time-varying device among the plurality of time-varying devices, and determining a storage space for replacement, based on the output signal.Type: ApplicationFiled: November 16, 2023Publication date: January 30, 2025Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Shinhyun CHOI, Myoungsoo Jung, Hakcheon Jeong, See-On Park, Donghyun Gouk, Seonghyeon Jang
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Patent number: 12210744Abstract: An accelerator includes a processor and a hybrid memory system. The hybrid memory system includes a resistance-based non-volatile memory, a DRAM used as a cache of the resistance-based non-volatile memory, a non-volatile memory controller connected to the resistance-based non-volatile memory and configured to control the DRAM and the resistance-based non-volatile memory, a memory controller configured to process a memory request from the processor and control the DRAM, and a memory channel configured to connect the DRAM, the non-volatile memory controller, and the memory controller.Type: GrantFiled: December 29, 2022Date of Patent: January 28, 2025Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Myoungsoo Jung, Jie Zhang, Hanyeoreum Bae
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Patent number: 12169636Abstract: A computational storage supporting graph machine learning acceleration includes a solid state drive (SSD) configured to store a graph data set; and a field-programmable gate array (FPGA) configured to download, to a memory, a graph machine learning model programmed in a form of a data flow graph by a host, wherein a hardware logic built in the FPGA performs access to the SSD through a peripheral component interconnect-express (PCIe) switch.Type: GrantFiled: January 9, 2023Date of Patent: December 17, 2024Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Myoungsoo Jung, Miryeong Kwon, Donghyun Gouk
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Publication number: 20240303122Abstract: Provided is an apparatus for accelerating graph neural network (GNN) pre-processing, the apparatus including a set-partitioning accelerator configured to sort each edge of an original graph stored in a coordinate list (COO) format by a node number, perform radix sorting based on a vertex identification (VID) to generate a COO array of a preset length, and perform uniform random sampling on some nodes of a given node array, a merger configured to merge the COO array of the preset length to generate one sorted COO array, a re-indexer configured to assign new consecutive VIDs respectively to the nodes selected through the uniform random sampling, and a compressed sparse row (CSR) converter configured to the edges sorted by the node number into a CSR format.Type: ApplicationFiled: August 22, 2023Publication date: September 12, 2024Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGInventors: Myoungsoo JUNG, Seungkwan Kang, Donghyun Gouk, Miryeong Kwon, Hyunkyu CHOI, Junhyeok Jang
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Publication number: 20240281645Abstract: Provided is an apparatus for accelerating graph neural network (GNN) pre-processing, the apparatus including a conversion unit configured to convert an original graph in a coordinate list (COO) format into a graph in a compressed sparse row (CSR) format, a sub-graph generation unit configured to generate a sub-graph with a reduced degree of the graph in the CSR format, and an embedding table generation unit configured to generate an embedding table corresponding to the sub-graph.Type: ApplicationFiled: August 16, 2023Publication date: August 22, 2024Applicant: Korea Advanced Institute of Science and TechnologyInventors: Myoungsoo JUNG, Seungkwan Kang, Donghyun Gouk, Miryeong Kwon, Hyunkyu Choi, Junhyeok Jang
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Publication number: 20240264957Abstract: A compute express link (CXL) computing system includes a host device including a CPU that supports CXL, and a CXL storage connected to a CXL root port of the CPU based on the CXL interconnect and including a flash memory-based memory module.Type: ApplicationFiled: January 29, 2024Publication date: August 8, 2024Inventors: Myoungsoo JUNG, Donghyun GOUK, Miryeong KWON
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Patent number: 11921628Abstract: A data storage device includes one or more nonvolatile memory devices each including a plurality of unit storage spaces; and an address recommending circuit configured to recommend a unit storage space among the plurality of unit storage spaces to process a write request, wherein the address recommending circuit applies feature data to a neural network to recommend the unit storage space, and wherein the feature data is generated based on request information for the write request, a target address corresponding to the write request, an address of data stored in the plurality of unit storage spaces.Type: GrantFiled: August 16, 2022Date of Patent: March 5, 2024Assignees: SK hynix Inc., Korea Advanced Institute of Science and TechnologyInventors: Junhyeok Jang, Seungkwan Kang, Dongsuk Oh, Myoungsoo Jung
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Publication number: 20240056191Abstract: An electronic system for transmitting and receiving internal data through an optical channel. The electronic system may include a light emitter configured to generate a first optical signal, a first device configured to receive the first optical signal and including a transmitter configured to output a second optical signal representing a transmission value based on the first optical signal, a second device including a first receiver configured to receive the second optical signal from the first device and output a third optical signal by adjusting a light intensity of the second optical signal, and configured to read the transmission value based on the light intensity of the second optical signal, and a third device including a second receiver configured to receive the third optical signal from the second device, and configured to read the transmission value based on a light intensity of the third optical signal.Type: ApplicationFiled: May 22, 2023Publication date: February 15, 2024Applicants: SAMSUNG ELECTRONICS CO., LTD., KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Hanyeoreum Bae, Myoungsoo Jung, Jie Zhang
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Publication number: 20240045588Abstract: An accelerator includes a processor and a hybrid memory system. The hybrid memory system includes a resistance-based non-volatile memory, a DRAM used as a cache of the resistance-based non-volatile memory, a non-volatile memory controller connected to the resistance-based non-volatile memory and configured to control the DRAM and the resistance-based non-volatile memory, a memory controller configured to process a memory request from the processor and control the DRAM, and a memory channel configured to connect the DRAM, the non-volatile memory controller, and the memory controller.Type: ApplicationFiled: December 29, 2022Publication date: February 8, 2024Inventors: Myoungsoo JUNG, Jie ZHANG, HANYEOREUM BAE
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Publication number: 20240012684Abstract: Disclosed is a memory disaggregation computing system including a host server and a memory device connected through a compute express link (CXL) network, in which a computing complex of the host server is connected to a memory resource of the memory device through a CXL packet transmitted through the CXL network, and executes an application program by using the memory resource.Type: ApplicationFiled: January 30, 2023Publication date: January 11, 2024Inventors: Myoungsoo JUNG, Donghyun GOUK
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Publication number: 20230418673Abstract: Provided is an apparatus for accelerating a graph neural network for efficient parallel processing of massive graph datasets, including a streaming multiprocess (SM) scheduler and a computation unit, wherein the SM scheduler obtains a subgraph and an embedding table per layer, determines a number of SMs to be allocated for processing embeddings of a destination-vertex based on a feature dimension and a maximum number of threads in each of the SMs, and allocates the determined number of SMs to each of all destination-vertices included in the subgraph, and the computation unit obtains, by each of the SMs, embeddings of a destination-vertex allocated to each SM, obtains, by each SM, embeddings of at least one or more neighbor-vertices of the destination-vertex using the subgraph, and performs, by each SM, a user-designated operation using the embeddings of the destination-vertex and the embeddings of the neighbor-vertices.Type: ApplicationFiled: February 9, 2023Publication date: December 28, 2023Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE ANDTECHNOLOGYInventors: Myoungsoo JUNG, Junhyeok JANG, Miryeong KWON, Donghyun GOUK, Hanyeoreum BAE
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Patent number: 11809317Abstract: A memory controlling device configured to connect to a memory module including a resistance switching memory cell array which is partitioned into a plurality of partitions including a first partition and a second partition is provided. A first controlling module accesses the memory module. A second controlling module determines whether there is a conflict for the first partition to which a read request targets when an incoming request is the read request, instructs the first controlling module to read target data of the read request from the memory module when a write to the second partition is in progress, and suspends the read request when a write to the first partition is in progress.Type: GrantFiled: February 24, 2022Date of Patent: November 7, 2023Assignees: MemRay Corporation, Yonsei University, University—Industry Foundation (UIF)Inventors: Myoungsoo Jung, Gyuyoung Park, Miryeong Kwon
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Publication number: 20230350797Abstract: A flash memory device of a flash-based storage device includes a plurality of flash buses and a plurality of flash memory chips, and each flash bus is connected to two or more flash memory chips among the flash memory chips. A front-end includes a processing core, and a plurality of flash controllers are respectively connected to the flash buses. Each flash controller includes a flash controller logic configured to perform a read operation or a write operation in a flash memory chip connected to a corresponding flash bus among the flash buses, and a router configured to perform communication with another flash controller among the flash controllers.Type: ApplicationFiled: August 12, 2022Publication date: November 2, 2023Inventors: JohnDongjun KIM, Jiho KIM, Myoungsoo JUNG
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Patent number: 11775452Abstract: In a non-volatile memory controlling device, a first doorbell region is exposed to a configuration space of a host interface and updated when the host issues an input/output (I/O) request command to the host memory. A fetch managing module fetches the command from the host memory in response to an event signal generated when the first doorbell region is updated. A data transferring module checks a location of the host memory based on request information included in the command, and performs a transfer of target data for the I/O request between the host memory and the non-volatile memory module. A completion handling module writes a completion request in the host memory and handles an interrupt when the data transferring module completes to process the I/O request. A second doorbell region is exposed to the configuration space and updated when the I/O service is terminated by the host.Type: GrantFiled: July 22, 2021Date of Patent: October 3, 2023Inventor: Myoungsoo Jung