Abstract: A display device includes a first transistor including a first active layer, a first gate electrode overlapping the first active layer, a gate insulating layer between the first active layer and the first gate electrode, a first source electrode, and a first drain electrode; a second transistor including a second active layer, a second gate electrode overlapping the second active layer, a second source electrode and a second drain electrode; a capacitor including a first capacitor electrode connected to the second transistor; a lower electrode disposed under the first active layer; a connecting member connecting the first active layer to the lower electrode; and a first metal pattern contacting the connecting member and disposed on a same layer with the first gate electrode.

Abstract: For analog to digital conversion with correlated double sampling in an image sensor, a pixel signal from a given pixel is sampled to generate a respective sampled signal N-times, with N>1 within a horizontal scan time period. A ramp signal is generated with a respective ramping portion for each respective sampled signal. Each respective sampled signal is compared with a respective ramping portion to generate a respective comparison signal that determines a respective digital code. The N respective digital codes are summed to generate a final digital code with reduced random noise.

Abstract: A CMOS image sensor may include an active pixel sensor array and a noise canceller array corresponding to the active pixel sensor array. A method of operating such an CMOS image sensor may involve generating a varying reference signal that mirrors noise external to the active pixel sensor array, outputting the varying reference signal to the noise canceller array, and using the varying reference signal in the noise canceller array to cancel noise both internal to and external to the active pixel sensor array.

Abstract: An apparatus for canceling a fixed pattern noise in a CMOS image sensor includes a storage device, a fixed pattern noise operation circuit, and a fixed pattern noise canceling circuit. The storage device stores first reference fixed pattern noises operated in a vertical blank section of an (n?1)th frame. The fixed pattern noise operation circuit calculates second reference fixed pattern noises based on the first reference fixed pattern noises stored in the storage device and blank fixed pattern noises output in a vertical blank section of an n-th frame and outputs the second reference fixed pattern noises to the storage device to update the first reference fixed pattern noises to the second reference fixed pattern noises.

Abstract: An image pick-up device includes a first correlated double sampling circuit configured to generate a first sampling signal by performing correlated double sampling on an active pixel signal output from an active pixel and generating a first comparison signal by comparing the first sampling signal with a reference signal, and a second correlated double sampling circuit to generate a second sampling signal by performing correlated double sampling on an OB pixel signal output from an optical black pixel and generating a second comparison signal by comparing the second sampling signal with the reference signal.

Abstract: A CMOS image sensor may include an active pixel sensor array and a noise canceller array corresponding to the active pixel sensor array. A method of operating such an CMOS image sensor may involve generating a varying reference signal that mirrors noise external to the active pixel sensor array, outputting the varying reference signal to the noise canceller array, and using the varying reference signal in the noise canceller array to cancel noise both internal to and external to the active pixel sensor array.

Abstract: An image pick-up device includes a first correlated double sampling circuit configured to generate a first sampling signal by performing correlated double sampling on an active pixel signal output from an active pixel and generating a first comparison signal by comparing the first sampling signal with a reference signal, and a second correlated double sampling circuit to generate a second sampling signal by performing correlated double sampling on an OB pixel signal output from an optical black pixel and generating a second comparison signal by comparing the second sampling signal with the reference signal.

Abstract: An apparatus for canceling a fixed pattern noise in a CMOS image sensor includes a storage device, a fixed pattern noise operation circuit, and a fixed pattern noise canceling circuit. The storage device stores first reference fixed pattern noises operated in a vertical blank section of an (n?1)th frame. The fixed pattern noise operation circuit calculates second reference fixed pattern noises based on the first reference fixed pattern noises stored in the storage device and blank fixed pattern noises output in a vertical blank section of an n-th frame and outputs the second reference fixed pattern noises to the storage device to update the first reference fixed pattern noises to the second reference fixed pattern noises.

Abstract: An analog-to-digital converter includes an amplifying unit and a noise compensation unit. The amplifying unit amplifies a difference between a trip point voltage and a modified signal voltage. The trip point voltage has a first power noise component, and the noise compensation unit incorporates a second power noise component into an original signal voltage to generate the modified signal voltage. Thus, the power noise components are cancelled in the difference.

Abstract: For analog to digital conversion with correlated double sampling in an image sensor, a pixel signal from a given pixel is sampled to generate a respective sampled signal N-times, with N>1 within a horizontal scan time period. A ramp signal is generated with a respective ramping portion for each respective sampled signal. Each respective sampled signal is compared with a respective ramping portion to generate a respective comparison signal that determines a respective digital code. The N respective digital codes are summed to generate a final digital code with reduced random noise.

Abstract: An analog-to-digital converter includes a comparator, a latch, and a bias control unit. The comparator is turned on by an applied bias voltage for comparing an analog voltage with a ramp voltage. The latch activates an end signal when the ramp voltage becomes greater than the analog voltage as indicated by the comparator. The bias control unit uncouples the bias voltage from the comparator when the end signal is activated for reducing power consumption.

Abstract: A CMOS image sensor may include an active pixel sensor array and a noise canceller array corresponding to the active pixel sensor array. A method of operating such an CMOS image sensor may involve generating a varying reference signal that mirrors noise external to the active pixel sensor array, outputting the varying reference signal to the noise canceller array, and using the varying reference signal in the noise canceller array to cancel noise both internal to and external to the active pixel sensor array.

Abstract: An analog-to-digital converter includes a comparator, a latch, and a bias control unit. The comparator is turned on by an applied bias voltage for comparing an analog voltage with a ramp voltage. The latch activates an end signal when the ramp voltage becomes greater than the analog voltage as indicated by the comparator. The bias control unit uncouples the bias voltage from the comparator when the end signal is activated for reducing power consumption.

Abstract: An analog-to-digital converter includes an amplifying unit and a noise compensation unit. The amplifying unit amplifies a difference between a trip point voltage and a modified signal voltage. The trip point voltage has a first power noise component, and the noise compensation unit incorporates a second power noise component into an original signal voltage to generate the modified signal voltage. Thus, the power noise components are cancelled in the difference.

Abstract: A phase locked loop (PLL) for reducing electromagnetic interference (EMI) is provided. The PLL is not sensitive to a manufacturing process, consumes less power, occupies a small layout space, and can flexibly control a modulation frequency and a modulation rate flexibly. The PLL for reducing the EMI controls the signals having a phase difference, which is n-times (where n is an integer) the basic delay time of the output signals from a voltage controlled oscillator (VCO), and determines the modulation rate. Then, the PLL repeats the procedure during the cycle of a pre-defined modulation frequency. The PLL for reducing the EMI not only reduces the EMI, but also does not require a ROM. Therefore, the layout space can be reduced and broad frequency ranges can be obtained. In addition, since the phase difference of the output signals of the VCO is controlled by logic circuits, the PLL is insensitive to changes in the manufacturing process.

Abstract: A phase locked loop (PLL) for reducing electromagnetic interference (EMI) is provided. The PLL is not sensitive to a manufacturing process, consumes less power, occupies a small layout space, and can flexibly control a modulation frequency and a modulation rate flexibly. The PLL for reducing the EMI controls the signals having a phase difference, which is n-times (where n is an integer) the basic delay time of the output signals from a voltage controlled oscillator (VCO), and determines the modulation rate. Then, the PLL repeats the procedure during the cycle of a pre-defined modulation frequency. The PLL for reducing the EMI not only reduces the EMI, but also does not require a ROM. Therefore, the layout space can be reduced and broad frequency ranges can be obtained. In addition, since the phase difference of the output signals of the VCO is controlled by logic circuits, the PLL is insensitive to changes in the manufacturing process.