Abstract: A semiconductor memory includes: first column lines extending in a first direction; first row lines extending in a second direction; first memory cells located between the first row lines and the first column lines; second column lines electrically connected to the first column lines; second row lines extending in the second direction; and second memory cells located between the second row lines and the second column lines. The first column lines and the second column lines may overlap with each other in a third direction. In a first region, current paths on the second row lines are shorter than current paths on the second row lines in a second region. An overlapping ratio of a second column line belonging to the first region with a first column line may be smaller than that of a second column line belonging to the second region with another first column line.

Abstract: A semiconductor memory includes: first column lines extending in a first direction; first row lines extending in a second direction; first memory cells located between the first row lines and the first column lines; second column lines electrically connected to the first column lines; second row lines extending in the second direction; and second memory cells located between the second row lines and the second column lines. The first column lines and the second column lines may overlap with each other in a third direction. In a first region, current paths on the second row lines are shorter than current paths on the second row lines in a second region. An overlapping ratio of a second column line belonging to the first region with a first column line may be smaller than that of a second column line belonging to the second region with another first column line.

Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory includes a first metal oxide layer disposed over a substrate and including a trench therein, a second metal oxide layer disposed along an inner wall of the trench, a selector disposed over the second metal oxide layer and buried in a part of the trench, and a top electrode disposed over the selector.

Abstract: A phase-change random access memory device includes a semiconductor substrate, an interlayer dielectric layer formed over the semiconductor substrate and having contact holes defined therein, metal contacts formed in the contact holes, an ohmic contact layer formed over the metal contacts and having recesses defined therein, and switching elements formed over the recesses of the ohmic contact layer.

Abstract: A phase-change random access memory device includes a semiconductor substrate, an interlayer dielectric layer formed over the semiconductor substrate and having contact holes defined therein, metal contacts formed in the contact holes, an ohmic contact layer formed over the metal contacts and having recesses defined therein, and switching elements formed over the recesses of the ohmic contact layer.

Abstract: A phase shift mask and a method for fabricating the same are provided. The phase shift mask includes: a substrate; a multiple thin layer structure formed over the substrate, the multiple thin layer structure including an opening formed to a predetermined depth; and an absorption material filling a portion of the opening. The method includes: preparing a substrate; forming a multiple thin layer structure over the substrate; etching a portion of the multiple thin layer structure to form an opening; and filling a portion of the opening with an absorption material.