Abstract: A composition for inhibiting sodium leakage channel (NALCN), including as an active ingredient N-benzhydryl quinuclidine (NBQN) or a N-benzhydryl quinuclidine derivative represented by the following Formula 1, wherein in the following Formula 1, R is an unsubstituted or substituted benzyl group

Abstract: A composition for inhibiting sodium leakage channel (NALCN), including as an active ingredient N-benzhydryl quinuclidine (NBQN) or a N-benzhydryl quinuclidine derivative represented by the following Formula 1, wherein in the following Formula 1, R is an unsubstituted or substituted benzyl group

Abstract: An image sensor includes a first semiconductor layer having a first semiconductor region and a first insulating region, and a second semiconductor layer under the first semiconductor layer including a second semiconductor region and a second insulating region. The first semiconductor layer includes a first transistor having first source or drain regions in the first semiconductor region and a first gate electrode in the first insulating region, a contact wiring, a first wiring layer electrically connecting the contact wiring and the first transistor, and a first junction region electrically connected to the first wiring layer. The second semiconductor layer includes a second transistor having second source or drain regions in the second semiconductor region and a second gate electrode in the second insulating region, a second wiring layer electrically connecting the contact wiring and the second transistor, and a second junction region electrically connected to the second wiring layer.

Abstract: A semiconductor device having a high and stable operating voltage and a method of manufacturing the same, the semiconductor device including: a substrate having an active region including a channel region; a gate insulating layer that covers a top surface of the active region; a gate electrode that covers the gate insulating layer on the top surface of the active region; buried insulating patterns in the channel region of the active region at a lower side of the gate electrode and spaced apart from a top surface of the substrate; and a pair of source/drain regions in the substrate at both sides of each of the buried insulating patterns and extending from the top surface of the substrate to a level lower than that of each of the buried insulating patterns.

Abstract: An image sensor includes a first semiconductor layer having a first semiconductor region and a first insulating region, and a second semiconductor layer under the first semiconductor layer including a second semiconductor region and a second insulating region. The first semiconductor layer includes a first transistor having first source or drain regions in the first semiconductor region and a first gate electrode in the first insulating region, a contact wiring, a first wiring layer electrically connecting the contact wiring and the first transistor, and a first junction region electrically connected to the first wiring layer. The second semiconductor layer includes a second transistor having second source or drain regions in the second semiconductor region and a second gate electrode in the second insulating region, a second wiring layer electrically connecting the contact wiring and the second transistor, and a second junction region electrically connected to the second wiring layer.

Abstract: An integrated circuit device includes a substrate including a first region and a second region, a first transistor in the first region, the first transistor being an N-type transistor and including a first silicon-germanium layer on the substrate, and a first gate electrode on the first silicon-germanium layer, and a second transistor in the second region and including a second gate electrode, the second transistor not having a silicon-germanium layer between the substrate and the second gate electrode.

Abstract: A semiconductor device having a high and stable operating voltage and a method of manufacturing the same, the semiconductor device including: a substrate having an active region including a channel region; a gate insulating layer that covers a top surface of the active region; a gate electrode that covers the gate insulating layer on the top surface of the active region; buried insulating patterns in the channel region of the active region at a lower side of the gate electrode and spaced apart from a top surface of the substrate; and a pair of source/drain regions in the substrate at both sides of each of the buried insulating patterns and extending from the top surface of the substrate to a level lower than that of each of the buried insulating patterns.

Abstract: An integrated circuit device includes a substrate including a first region and a second region, a first transistor in the first region, the first transistor being an N-type transistor and including a first silicon-germanium layer on the substrate, and a first gate electrode on the first silicon-germanium layer, and a second transistor in the second region and including a second gate electrode, the second transistor not having a silicon-germanium layer between the substrate and the second gate electrode.

Abstract: A nonvolatile memory device including a cell array area in which a plurality of unit cells are arranged at least in one direction includes a plurality of memory transistors formed in the respective unit cells. Each memory transistor includes a gate pattern in which a tunnel insulating layer, a floating gate, an inter-gate insulating layer, and a control gate are laminated, and first and second junction areas arranged on opposite sides of the gate pattern, wherein the gate patterns are separated in the one direction by unit cells. The nonvolatile memory device also includes a first conduction interconnection which extends in the one direction and is arranged in a position that overlaps the control gate and a plurality of first contacts, at least one of which is arranged for each of the control gates to connect the control gates and the first conduction interconnection.

Abstract: A method of fabricating a semiconductor device includes forming a device isolation region on a semiconductor substrate to define an active region, forming a gate electrode on the active region and the device isolation region across the active region, and forming at least one gate electrode opening portion in the gate electrode so as to overlap an edge portion of the active region, wherein the gate electrode opening portion is simultaneously formed with the gate electrode.

Abstract: Semiconductor device having an on-chip type electrostatic discharge (ESD) protection circuit and a method of manufacturing the same are provided. The on-chip type ESD protection circuit may include a first junction diode having a first conductive type region contacting a second conductive type region in a semiconductor substrate, and a first schottky diode having a metallic material layer arranged on and contacting the first conductive type region of the semiconductor substrate.

Abstract: A method of fabricating a semiconductor device includes forming a device isolation region on a semiconductor substrate to define an active region, forming a gate electrode on the active region and the device isolation region across the active region, and forming at least one gate electrode opening portion in the gate electrode so as to overlap an edge portion of the active region, wherein the gate electrode opening portion is simultaneously formed with the gate electrode.

Abstract: A non-volatile memory device includes; a first well having a first impurity concentration formed in a first region of a semiconductor substrate, a second well having a second impurity concentration different from the first impurity concentration formed in a second region of the semiconductor substrate, an access transistor with floating gate formed on the first region, and a control Metal Oxide Semiconductor (MOS) capacitor with one electrode formed on the second region.

Abstract: A nonvolatile memory device including a cell array area in which a plurality of unit cells are arranged at least in one direction includes a plurality of memory transistors formed in the respective unit cells. Each memory transistor includes a gate pattern in which a tunnel insulating layer, a floating gate, an inter-gate insulating layer, and a control gate are laminated, and first and second junction areas arranged on opposite sides of the gate pattern, wherein the gate patterns are separated in the one direction by unit cells. The to nonvolatile memory device also includes a first conduction interconnection which extends in the one direction and is arranged in a position that overlaps the control gate and a plurality of first contacts, at least one of which is arranged for each of the control gates to connect the control gates and the first conduction interconnection.

Abstract: A semiconductor integrated circuit device includes: an electrostatic discharge (ESD) impurity region formed in a substrate; a bump formed on the substrate; and a first wiring layer and a second wiring layer formed at the same level under the bump. The first and second wiring layers are separated from each other, and at least part of each of the first and second wiring layers are overlapped by the bump. The first wiring layer is electrically connected to the ESD impurity region and the bump, and the second wiring layer is insulated from the bump.

Abstract: A nonvolatile memory device including a plurality of word lines; a plurality of bit lines intersecting the word lines; a plurality of memory cells corresponding to intersections of the word lines and the bit lines; a common control gate line commonly connected to the memory cells; and a common erasing gate line commonly connected to the memory cells.

Abstract: Semiconductor device having an on-chip type electrostatic discharge (ESD) protection circuit and a method of manufacturing the same are provided. The on-chip type ESD protection circuit may include a first junction diode having a first conductive type region contacting a second conductive type region in a semiconductor substrate, and a first schottky diode having a metallic material layer arranged on and contacting the first conductive type region of the semiconductor substrate.

Abstract: The present invention provides a method for forming a field oxide film on a semiconductor device. In particular, the present invention provides a method for forming a field oxide film on a semiconductor device using a silicon epitaxial layer to improve a Shallow Trench Isolation (STI) process.

Abstract: A semiconductor device having a recessed silicon on insulator (SOI) structure includes an SOI substrate having a cell region, a peripheral region and a field region, the SOI substrate having a first semiconductor layer, an insulating layer on the first semiconductor layer, and a second semiconductor layer on the insulating layer, a trench in the field region of the second semiconductor layer, a device isolation film within the trench, a peripheral region recessed in the second semiconductor layer, and an active semiconductor device on the cell region and the peripheral region of the second semiconductor layer.

Abstract: The present invention provides a method for forming a field oxide film on a semiconductor device. In particular, the present invention provides a method for forming a field oxide film on a semiconductor device using a silicon epitaxial layer to improve a Shallow Trench Isolation (STI) process.