Patents by Inventor Myoungkyun KIL

Myoungkyun KIL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9978694
    Abstract: Disclosed are a semiconductor package and a method of fabricating the same. The semiconductor package includes a first substrate, and a first semiconductor chip positioned above the first substrate. A second semiconductor chip is positioned above a top surface of the first semiconductor chip. An adhesive layer is between the first semiconductor chip and the second semiconductor chip. A second substrate is disposed on the second semiconductor chip. The second substrate substantially covers a top surface of the second semiconductor chip. A mold layer is disposed between the first substrate and the second substrate.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: May 22, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyongsoon Cho, Myoungkyun Kil, Hansung Ryu
  • Publication number: 20180068958
    Abstract: Disclosed are a semiconductor package and a method of fabricating the same. The semiconductor package includes a first substrate, and a first semiconductor chip positioned above the first substrate. A second semiconductor chip is positioned above a top surface of the first semiconductor chip. An adhesive layer is between the first semiconductor chip and the second semiconductor chip. A second substrate is disposed on the second semiconductor chip. The second substrate substantially covers a top surface of the second semiconductor chip. A mold layer is disposed between the first substrate and the second substrate.
    Type: Application
    Filed: April 24, 2017
    Publication date: March 8, 2018
    Inventors: KYONGSOON CHO, MYOUNGKYUN KIL, HANSUNG RYU
  • Publication number: 20160379937
    Abstract: A substrate strip is provided. The substrate strip includes a core layer including first and second substrate regions spaced apart from each other and a dummy region between the first and second substrate regions, a first interconnection layer disposed on top surfaces of the first and second substrate regions, a second interconnection layer disposed on bottom surfaces of the first and second substrate regions, and a warpage control member provided on any one of a top surface and a bottom surface of the dummy region. The warpage control member includes a metal.
    Type: Application
    Filed: April 26, 2016
    Publication date: December 29, 2016
    Inventors: KyongSoon CHO, Myoungkyun KIL, Hansung RYU