Abstract: A data storage device includes one or more nonvolatile memory devices each including a plurality of unit storage spaces; and an address recommending circuit configured to recommend a unit storage space among the plurality of unit storage spaces to process a write request, wherein the address recommending circuit applies feature data to a neural network to recommend the unit storage space, and wherein the feature data is generated based on request information for the write request, a target address corresponding to the write request, an address of data stored in the plurality of unit storage spaces.

Abstract: An electronic system for transmitting and receiving internal data through an optical channel. The electronic system may include a light emitter configured to generate a first optical signal, a first device configured to receive the first optical signal and including a transmitter configured to output a second optical signal representing a transmission value based on the first optical signal, a second device including a first receiver configured to receive the second optical signal from the first device and output a third optical signal by adjusting a light intensity of the second optical signal, and configured to read the transmission value based on the light intensity of the second optical signal, and a third device including a second receiver configured to receive the third optical signal from the second device, and configured to read the transmission value based on a light intensity of the third optical signal.

Abstract: An accelerator includes a processor and a hybrid memory system. The hybrid memory system includes a resistance-based non-volatile memory, a DRAM used as a cache of the resistance-based non-volatile memory, a non-volatile memory controller connected to the resistance-based non-volatile memory and configured to control the DRAM and the resistance-based non-volatile memory, a memory controller configured to process a memory request from the processor and control the DRAM, and a memory channel configured to connect the DRAM, the non-volatile memory controller, and the memory controller.

Abstract: Disclosed is a memory disaggregation computing system including a host server and a memory device connected through a compute express link (CXL) network, in which a computing complex of the host server is connected to a memory resource of the memory device through a CXL packet transmitted through the CXL network, and executes an application program by using the memory resource.

Abstract: Provided is an apparatus for accelerating a graph neural network for efficient parallel processing of massive graph datasets, including a streaming multiprocess (SM) scheduler and a computation unit, wherein the SM scheduler obtains a subgraph and an embedding table per layer, determines a number of SMs to be allocated for processing embeddings of a destination-vertex based on a feature dimension and a maximum number of threads in each of the SMs, and allocates the determined number of SMs to each of all destination-vertices included in the subgraph, and the computation unit obtains, by each of the SMs, embeddings of a destination-vertex allocated to each SM, obtains, by each SM, embeddings of at least one or more neighbor-vertices of the destination-vertex using the subgraph, and performs, by each SM, a user-designated operation using the embeddings of the destination-vertex and the embeddings of the neighbor-vertices.

Abstract: A memory controlling device configured to connect to a memory module including a resistance switching memory cell array which is partitioned into a plurality of partitions including a first partition and a second partition is provided. A first controlling module accesses the memory module. A second controlling module determines whether there is a conflict for the first partition to which a read request targets when an incoming request is the read request, instructs the first controlling module to read target data of the read request from the memory module when a write to the second partition is in progress, and suspends the read request when a write to the first partition is in progress.

Abstract: A flash memory device of a flash-based storage device includes a plurality of flash buses and a plurality of flash memory chips, and each flash bus is connected to two or more flash memory chips among the flash memory chips. A front-end includes a processing core, and a plurality of flash controllers are respectively connected to the flash buses. Each flash controller includes a flash controller logic configured to perform a read operation or a write operation in a flash memory chip connected to a corresponding flash bus among the flash buses, and a router configured to perform communication with another flash controller among the flash controllers.

Abstract: In a non-volatile memory controlling device, a first doorbell region is exposed to a configuration space of a host interface and updated when the host issues an input/output (I/O) request command to the host memory. A fetch managing module fetches the command from the host memory in response to an event signal generated when the first doorbell region is updated. A data transferring module checks a location of the host memory based on request information included in the command, and performs a transfer of target data for the I/O request between the host memory and the non-volatile memory module. A completion handling module writes a completion request in the host memory and handles an interrupt when the data transferring module completes to process the I/O request. A second doorbell region is exposed to the configuration space and updated when the I/O service is terminated by the host.

Abstract: A data storage device includes one or more nonvolatile memory devices each including a plurality of unit storage spaces; and an address recommending circuit configured to recommend a unit storage space among the plurality of unit storage spaces to process a write request, wherein the address recommending circuit applies feature data to a neural network to recommend the unit storage space, and wherein the feature data is generated based on request information for the write request, a target address corresponding to the write request, an address of data stored in the plurality of unit storage spaces.

Abstract: A computational storage supporting graph machine learning acceleration includes a solid state drive (SSD) configured to store a graph data set; and a field-programmable gate array (FPGA) configured to download, to a memory, a graph machine learning model programmed in a form of a data flow graph by a host, wherein a hardware logic built in the FPGA performs access to the SSD through a peripheral component interconnect-express (PCIe) switch.

Abstract: A first IP address is set to the host, and a second IP address is set to the storage card. A storage card includes a storage device and a processor for executing firmware. The host converts a first Ethernet packet including an ISP-related request and destined for the second IP address into an NVMe request according to an NVMe protocol, and transfers the NVMe request to the storage card. The firmware parses the NVMe request to perform the ISP-related request.

Abstract: A method of supporting persistence of a computing device is provided. The computing device performs a stop procedure upon power failure. In the stop procedure, the computing device schedules out a running process task, stores a state of the process task to a process control block of a memory module including a non-volatile memory, flushes a cache for the processor, and flushes a pending memory request.

Abstract: A first IP address is set to the host, and a second IP address is set to the storage card. A storage card includes a storage device and a processor for executing firmware. The host converts a first Ethernet packet including an ISP-related request and destined for the second IP address into an NVMe request according to an NVMe protocol, and transfers the NVMe request to the storage card. The firmware parses the NVMe request to perform the ISP-related request.

Abstract: A processor of the computing device includes a plurality of cores and executes one or more instructions stored in a memory module including a non-volatile memory, thereby performing a stop procedure upon a power failure and performing a go procedure upon power recovery. In the stop procedure, the processor accesses process control blocks of processes being run, scheduling each process to a run queue of a corresponding first core among first cores included in the cores, removes the scheduled process from the run queue and makes the removed process wait in a waiting queue, executes an idle task, and stops a device included in the computing device.

Abstract: A method for operating a graph processing system including a first and second memory, comprising: storing in the first memory, a start index, a terminal index and an edge value of graph data; storing in the second memory, a start vertex of the graph data; rearranging the start vertex as an intermediate vertex by using to the start index; performing a graph computation on the intermediate vertex by using to the terminal index and the edge value; storing in the second memory, a terminal vertex as a result of the graph computation; determining whether a graph processing operation is completed by comparing the terminal vertex and the start vertex; setting the terminal vertex as the start vertex when the graph processing operation is not completed; and iterating the rearranging, the performing, the storing the terminal vertex, the determining and the setting until the graph processing operation is completed.

Abstract: A memory controlling device configured to connect to a memory module including a resistance switching memory cell array which is partitioned into a plurality of partitions including a first partition and a second partition is provided. A first controlling module accesses the memory module. A second controlling module determines whether there is a conflict for the first partition to which a read request targets when an incoming request is the read request, instructs the first controlling module to read target data of the read request from the memory module when a write to the second partition is in progress, and suspends the read request when a write to the first partition is in progress.

Abstract: An electronic device is provided. A memory controller, having an improved response time for an input/output request and increased capacity of Dynamic Random Access Memory (DRAM) according to the present disclosure, includes an available-time prediction component configured to perform a machine learning operation using a Recurrent Neural Network (RNN) model based on input/output request information about an input/output request input from a host, and to predict an idle time representing a time during which the input/output request is not expected to be input from the host and a data compression controller configured to generate, in response to the idle time longer than a set reference time, compressed map data by compressing map data which indicates a mapping relationship between a logical address provided by the host and a physical address indicating a physical location of a memory block included in the memory device.

Abstract: A memory controlling device configured to connect to a memory module including a resistance switching memory cell array which is partitioned into a plurality of partitions including a first partition and a second partition is provided. A first controlling module accesses the memory module. A second controlling module determines whether there is a conflict for the first partition to which a read request targets when an incoming request is the read request, instructs the first controlling module to read target data of the read request from the memory module when a write to the second partition is in progress, and suspends the read request when a write to the first partition is in progress.

Abstract: Provided herein is a storage node of a distributed storage system and a method of operating the same. A memory controller may include a data controller configured to receive a write request and write data corresponding to the write request from a host, and configured to determine a physical address of a memory block in which the write data is to be stored based on chunk type information included in the write request, a memory control component configured to provide a program command for instructing the memory block to store the write data, the physical address, and the write data to the memory device, wherein the chunk type information is information about whether the write data indicates a type of data chunks or a type of coding chunks, the data chunks and the coding chunks being generated by the host performing an erasure coding operation on original data.

Abstract: In a storage card, a first module exposes a set of registers including a first register to the host through a configuration space of a host interface, and the first register is written when the host submits a command of an I/O request to the host memory. A second module fetches the command from the host memory when the first register is written. A third module detects a location of the host memory based on a host memory address of request information in response to signaling of the second module, and performs a transfer of target data between the host memory and a memory controller. A fourth module writes a completion event to the host memory through the configuration space in response to service completion of the I/O request in the third module, and informs the host about I/O completion by writing an interrupt.