Patents by Inventor Myra MCDONNELL

Myra MCDONNELL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11056356
    Abstract: Techniques and mechanisms for bonding a first wafer to a second wafer in the presence of a fluid, the viscosity of which is greater than a viscosity of air at standard ambient temperature and pressure. In an embodiment, a first surface of the first wafer is brought into close proximity to a second surface of the second wafer. The fluid is provided between the first surface and the second surface when a first region of the first surface is made to contact a second region of the second surface to form a bond. The viscosity of the fluid mitigates a rate of propagation of the bond along a wafer surface, which in turn mitigates wafer deformation and/or stress between wafers. In another embodiment, the viscosity of the fluid is changed dynamically while the bond propagates between the first surface and the second surface.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventors: Brennen K. Mueller, Daniel Pantuso, Mauro J. Kobrinsky, Chytra Pawashe, Myra McDonnell
  • Publication number: 20200303191
    Abstract: Embodiments herein describe techniques for bonded wafers that includes a first wafer bonded with a second wafer, and a stress compensation layer in contact with the first wafer or the second wafer. The first wafer has a first stress level at a first location, and a second stress level different from the first stress level at a second location. The stress compensation layer includes a first material at a first location of the stress compensation layer that induces a third stress level at the first location of the first wafer, a second material different from the first material at a second location of the stress compensation layer that induces a fourth stress level different from the third stress level at the second location of the first wafer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 18, 2019
    Publication date: September 24, 2020
    Inventors: Anant JAHAGIRDAR, Chytra PAWASHE, Aaron LILAK, Myra MCDONNELL, Brennen MUELLER, Mauro KOBRINSKY
  • Patent number: 10720345
    Abstract: Techniques and mechanisms for forming a bond between two wafers. In an embodiment, a first wafer and a second wafer are positioned with respective wafer holders, and are deformed to form a first deformation of the first wafer and a second deformation of the second wafer. The first deformation and the second deformation are symmetrical with respect to a centerline which is between the first wafer and the second wafer. A portion of the first deformation is made to contact, and form a bond with, another portion of the second deformation. The bond is propagated along respective surfaces of the wafers to form a coupling therebetween. In another embodiment, one of the wafer holders comprises one of an array of elements to locally heat or cool a wafer, or an array of displacement stages to locally deform said wafer.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: July 21, 2020
    Assignee: Intel Corporation
    Inventors: Mauro J. Kobrinsky, Myra McDonnell, Brennen K. Mueller, Chytra Pawashe, Daniel Pantuso, Paul B. Fischer, Lance C. Hibbeler, Martin Weiss
  • Patent number: 10707186
    Abstract: Techniques and mechanisms for forming a bond between wafers using a compliant layer. In an embodiment, a layer or layers of one or more compliant materials is provided on a first surface of a first wafer, and the one or more compliant layers are subsequently bonded to a second surface of a second wafer. The bonded wafers are heated to an elevated temperature at which a compliant layer exhibits non-elastic deformations to facilitate relaxation of stresses caused by wafer distortions. In another embodiment, a material of the compliant layer exhibits viscoelastic behavior at room temperature, wherein stress is mitigated by allowing wafer distortion to relax at room temperature.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Mauro J. Kobrinsky, Jasmeet S. Chawla, Stefan Meister, Myra McDonnell, Chytra Pawashe, Daniel Pantuso
  • Publication number: 20200075770
    Abstract: Integrated circuit structures having differentiated neighboring partitioned source or drain contact structures are described. An integrated circuit structure includes a first gate stack over a first fin, and a second gate stack over a second fin. First and second epitaxial source or drain structures are at first and second ends of the first fin. Third and fourth epitaxial source or drain structures are at first and second ends of the second fin. A first conductive contact structure is coupled to one of the first or the second epitaxial source or drain structures, and has a first portion partitioned from a second portion. A second conductive contact structure is coupled to one of the third or the fourth epitaxial source or drain structures, and has a first portion partitioned from a second portion. The second conductive contact structure is neighboring the first conductive contact structure and has a composition different than a composition of the first conductive contact structure.
    Type: Application
    Filed: September 5, 2018
    Publication date: March 5, 2020
    Inventors: Mauro J. KOBRINSKY, Stephanie BOJARSKI, Myra MCDONNELL, Tahir GHANI