Abstract: Mapping of neural network layers to physical neural cores is provided. In various embodiments, a neural network description describing a plurality of neural network layers is read. Each of the plurality of neural network layers has an associated weight tensor, input tensor, and output tensor. A plurality of precedence relationships among the plurality of neural network layers is determined. The weight tensor, input tensor, and output tensor of each of the plurality of neural network layers are mapped onto an array of neural cores.

Abstract: A neural network may include a set of components. The set of components may have timing requirements and a topological order. The relative timing of each component may be computed and the dependencies of the set of components may be enumerated. Mutable components within the set of components may be identified, and the relative timing of the mutable components may be adjusted to satisfy the timing requirements of each component in the set of components.

Abstract: Systems for neural network computation are provided. A neural network processor comprises a plurality of neural cores. The neural network processor has one or more processor precisions per activation. The processor is configured to accept data having a processor feature dimension. A transformation circuit is coupled to the neural network processor, and is adapted to: receive an input data tensor having an input precision per channel at one or more features; transform the input data tensor from the input precision to the processor precision; divide the input data into a plurality of blocks, each block conforming to one of the processor feature dimensions; provide each of the plurality of blocks to one of the plurality of neural cores. The neural network processor is adapted to compute, by the plurality of neural cores, output of one or more neural network layers.

Abstract: Networks for distributing parameters and data to neural network compute cores. In various embodiments, a neural inference chip comprises a plurality of neural cores and at least one network interconnecting the plurality of neural cores. Each of the plurality of neural cores is adapted to apply a plurality of synaptic weights to a plurality of input activations to produce a plurality of output activations. The at least one network is adapted to simultaneously deliver synaptic weights and/or input activations to the plurality of neural cores.

Abstract: Defect resistant designs for location-sensitive neural network processor arrays are provided. In various embodiments, plurality of neural network processor cores are arrayed in a grid. The grid has a plurality of rows and a plurality of columns. A network interconnects at least those of the plurality of neural network processor cores that are adjacent within the grid. The network is adapted to bypass a defective core of the plurality of neural network processor cores by providing a connection between two non-adjacent rows or columns of the grid, and transparently routing messages between the two non-adjacent rows or columns, past the defective core.

Abstract: Hardware neural network processors, are provided. A neural core includes a weight memory, an activation memory, a vector-matrix multiplier, and a vector processor. The vector-matrix multiplier is adapted to receive a weight matrix from the weight memory, receive an activation vector from the activation memory, and compute a vector-matrix multiplication of the weight matrix and the activation vector. The vector processor is adapted to receive one or more input vector from one or more vector source and perform one or more vector functions on the one or more input vector to yield an output vector. In some embodiments a programmable controller is adapted to configure and operate the neural core.

Abstract: The present invention relates to a method of manufacturing a plastic film (i.e. preferably a thermoplastic film), particularly a (thermo)plastic food packing film, especially a detectable (thermo)plastic film, which plastic film comprises detectable particles incorporated therein, as well as to the plastic film thus produced and to its applications and usages (i.e. its use).

Abstract: Neural network processing hardware using parallel computational architectures with reconfigurable core-level and vector-level parallelism is provided. In various embodiments, a neural network model memory is adapted to store a neural network model comprising a plurality of layers. Each layer has at least one dimension and comprises a plurality of synaptic weights. A plurality of neural cores is provided. Each neural core includes a computation unit and an activation memory. The computation unit is adapted to apply a plurality of synaptic weights to a plurality of input activations to produce a plurality of output activations. The computation unit has a plurality of vector units. The activation memory is adapted to store the input activations and the output activations. The system is adapted to partition the plurality of cores into a plurality of partitions based on dimensions of the layer and the vector units.

Abstract: The present invention relates to a multilayer film, especially to a multilayer thermoplastic film, which may be used for food packaging, wherein the multilayer film according to the present invention may be provided, on its inner side, with a food additive, particularly with a flavoring and/or coloring and/or an aroma producing food additive (such as e.g. a liquid smoke), which food additive is then released and transferred onto the surface of a foodstuff encased in the multilayer film during cooking and/or processing of the foodstuff.

Abstract: Instruction distribution in an array of neural network cores is provided. In various embodiments, a neural inference chip is initialized with core microcode. The chip comprises a plurality of neural cores. The core microcode is executable by the neural cores to execute a tensor operation of a neural network. The core microcode is distributed to the plurality of neural cores via an on-chip network. The core microcode is executed synchronously by the plurality of neural cores to compute a neural network layer.

Abstract: Hardware neural network processors, are provided. A neural core includes a weight memory, an activation memory, a vector-matrix multiplier, and a vector processor. The vector-matrix multiplier is adapted to receive a weight matrix from the weight memory, receive an activation vector from the activation memory, and compute a vector-matrix multiplication of the weight matrix and the activation vector. The vector processor is adapted to receive one or more input vector from one or more vector source and perform one or more vector functions on the one or more input vector to yield an output vector. In some embodiments a programmable controller is adapted to configure and operate the neural core.

Abstract: Neural inference chips are provided. A neural core of the neural inference chip comprises a vector-matrix multiplier; a vector processor; and an activation unit operatively coupled to the vector processor. The vector-matrix multiplier, vector processor, and/or activation unit is adapted to operate at variable precision.

Abstract: High-framerate real-time spatiotemporal disparity mechanisms on neuromorphic hardware are provided. In various embodiments, a first and second spiking input sensor each output a time series of spikes corresponding to a plurality of frames. A neurosynaptic network is configured to receive the time series of spikes corresponding to the plurality of frames; accumulate the time series of spikes in a ring buffer, thereby creating a plurality of temporal scales; for each corresponding pair of frames from the first and second spiking input sensors, determining a mapping of pixels in one of the pair of frames to pixels in the other of the pair of frames based on similarity; based on the pixel mapping, determining a disparity map.

Abstract: Hardware neural network processors, are provided. A neural core includes a weight memory, an activation memory, a vector-matrix multiplier, and a vector processor. The vector-matrix multiplier is adapted to receive a weight matrix from the weight memory, receive an activation vector from the activation memory, and compute a vector-matrix multiplication of the weight matrix and the activation vector. The vector processor is adapted to receive one or more input vector from one or more vector source and perform one or more vector functions on the one or more input vector to yield an output vector. In some embodiments a programmable controller is adapted to configure and operate the neural core.

Abstract: The present invention relates to a method of manufacturing a cellulosic film (cellulose film), particularly a cellulosic food packing film, especially a detectable cellulosic film, which cellulosic film comprises detectable particles incorporated therein, as well as to the cellulosic film thus produced and to its applications and usages (i.e. its use).

Abstract: A neural inference chip is provided, including at least one neural inference core. The at least one neural inference core is adapted to apply a plurality of synaptic weights to a plurality of input activations to produce a plurality of intermediate outputs. The at least one neural inference core comprises a plurality of activation units configured to receive the plurality of intermediate outputs and produce a plurality of activations. Each of the plurality of activation units is configured to apply a configurable activation function to its input. The configurable activation function has at least a re-ranging term and a scaling term, the re-ranging term determining the range of the activations and the scaling term determining the scale of the activations. Each of the plurality of activations units is configured to obtain the re-ranging term and the scaling term from one or more look up tables.

Abstract: High-framerate real-time spatiotemporal disparity mechanisms on neuromorphic hardware are provided. In various embodiments, a first and second spiking input sensor each output a time series of spikes corresponding to a plurality of frames. A neurosynaptic network is configured to receive the time series of spikes corresponding to the plurality of frames; accumulate the time series of spikes in a ring buffer, thereby creating a plurality of temporal scales; for each corresponding pair of frames from the first and second spiking input sensors, determining a mapping of pixels in one of the pair of frames to pixels in the other of the pair of frames based on similarity; based on the pixel mapping, determining a disparity map.

Abstract: The present invention relates to a multilayer film, especially to a multilayer thermoplastic film, which may be used for food packaging, wherein the multilayer film according to the present invention may be provided, on its inner side, with a food additive, particularly with a flavoring and/or coloring and/or an aroma producing food additive (such as e.g. a liquid smoke), which food additive is then released and transferred onto the surface of a foodstuff encased in the multilayer film during cooking and/or processing of the foodstuff.

Abstract: Edible cellulosic casings comprise cellulose and at least one modifier comprising at least one polysaccharide. The at least one modifier is substantially evenly distributed with the cellulose throughout a casing material of the edible cellulosic casing. A composition useful for an edible cellulosic casing comprises regenerated cellulose and at least one non-cellulose hydrophilic polysaccharide dispersed in the regenerated cellulose. The regenerated cellulose composes at least 50 wt. % of the composition. A method for forming an edible cellulosic casing comprises forming a cellulose solution and forming a modifier solution comprising at least one polysaccharide dissolved therein. The modifier and cellulose solutions are mixed to form a mixture from which the edible cellulosic casing is made. Edible cellulosic casings, as disclosed, may be consumed along with an encased foodstuff or other material for ingestion.

Abstract: Systems are provided that can produce symbolic and numeric representations of the neural network outputs, such that these outputs can be used to validate correctness of the implementation of the neural network. In various embodiments, a description of an artificial neural network containing no data-dependent branching is read. Based on the description of the artificial neural network, a symbolic representation is constructed of an output of the artificial neural network, the symbolic representation comprising at least one variable. The symbolic representation is compared to a ground truth symbolic representation, thereby validating the neural network system.