Abstract: A hybrid server and multi-layer switch system architecture, referred to hereinafter as the Enterprise Fabric (EF) architecture, forms the basis for a number of Enterprise Server (ES) chassis embodiments. Each ES embodiment generally includes one or more Processor Memory Modules (PMMs, each generally having one or more symmetric multiprocessor complexes), one or more Network Modules, and a System Control Module (SCM). The SCM includes a cellified switching-fabric core (SF) and a System Intelligence Module (SIM). Each PMM has one or more resident Virtual IO Controller (VIOC) adapters. Each VIOC is a specialized I/O controller that includes embedded layer-2 forwarding and filtering functions and tightly couples the PMM to the SF. Thus the layer-2 switch functionality within the ES chassis is distributed over all of the SCM, NM, and PMM modules.

Abstract: Virtual Network Interface Controllers (vNICs) provide for communication among modules of Enterprise Server (ES) embodiments via a switch fabric dataplane. Processes executing on compute complexes of the servers exchange data as packets or messages by interfaces made available through vNICs. The vNICs further provide for transparent communication with network and storage interfaces. vNIC provisioning capabilities include programmable bandwidth, priority scheme selection, and detailed priority control (such as round-robin weights). In some embodiments, vNICs are implemented in Virtual Input/Output Controllers (VIOCs). In another aspect, Virtual Local Area Networks (VLANs) enable access to layer-2 and selected layer-3 network functions while exchanging the packets and messages. VLAN identification is provided in each vNIC, and VLAN processing is partially performed in VIOCs implementing vNICs.

Abstract: A hybrid server and multi-layer switch system architecture, referred to hereinafter as the Enterprise Fabric (EF) architecture, forms the basis for a number of Enterprise Server (ES) chassis embodiments. Each ES embodiment generally includes one or more Processor Memory Modules (PMMs, each generally having one or more symmetric multiprocessor complexes), one or more Network Modules, and a System Control Module (SCM). The SCM includes a cellified switching-fabric core (SF) and a System Intelligence Module (SIM). Each PMM has one or more resident Virtual IO Controller (VIOC) adapters. Each VIOC is a specialized I/O controller that includes embedded layer-2 forwarding and filtering functions and tightly couples the PMM to the SF. Thus the layer-2 switch functionality within the ES chassis is distributed over all of the SCM, NM, and PMM modules.

Abstract: A hybrid server and multi-layer switch system architecture, referred to hereinafter as the Enterprise Fabric (EF) architecture, forms the basis for a number of Enterprise Server (ES) chassis embodiments. Each ES embodiment generally includes one or more Processor Memory Modules (PMMs, each generally having one or more symmetric multiprocessor complexes), one or more Network Modules, and a System Control Module (SCM). The SCM includes a cellified switching-fabric core (SF) and a System Intelligence Module (SIM). Each PMM has one or more resident Virtual IO Controller (VIOC) adapters. Each VIOC is a specialized I/O controller that includes embedded layer-2 forwarding and filtering functions and tightly couples the PMM to the SF. Thus the layer-2 switch functionality within the ES chassis is distributed over all of the SCM, NM, and PMM modules.

Abstract: A highly flexible and scalable architecture implements TDM bridge and related functions for network to telecom interface applications like voice over Internet. A very small packet size minimizes packetization delay so that VOIP can be realized without expensive echo cancellation. High density enables processing 4K simultaneous voice channels in real time on a single, compact circuit board.

Abstract: A highly flexible and scalable architecture implements TDM bridge and related functions for network to telecom interface applications like voice over Internet. A very small packet size minimizes packetization delay so that VOIP can be realized without expensive echo cancellation. High density enables processing 4K simultaneous voice channels in real time on a single, compact circuit board.