Patents by Inventor Myron J. Buer
Myron J. Buer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7940593Abstract: The present invention relates to a method and circuit for verifying the state of a gated fuse element used with a one-time programmable CMOS memory device. A first expected state is set and a state of a first gate-ox fuse is sensed. The state of the first gate-ox fuse is compared to the first expected state to determine if they are equal, and a first signal is generated. A second expected state is set and a state of a second gate-ox fuse is sensed. The state of the second gate-ox fuse is compared to the second expected state to determine if they are equal, and a second signal is generated. A valid output is generated if both the first and second signals are in a correct state, both signals are high for example.Type: GrantFiled: January 14, 2004Date of Patent: May 10, 2011Assignee: Broadcom CorporationInventors: Myron J. Buer, Douglas D. Smith
-
Patent number: 7897967Abstract: An anti-fuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A channel is formed between the source and drain regions. A gate and gate oxide are formed on the channel and lightly doped source and drain extension regions are formed in the channel. The lightly doped source and drain regions extend across the channel from the source and the drain regions, respectively, occupying a substantial portion of the channel. Programming of the anti-fuse is performed by application of power to the gate and at least one of the source region and the drain region to break-down the gate oxide, which minimizes resistance between the gate and the channel.Type: GrantFiled: March 31, 2005Date of Patent: March 1, 2011Assignee: Broadcom CorporationInventors: Akira Ito, Douglas D. Smith, Myron J. Buer
-
Patent number: 6902958Abstract: An anti-fuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A channel is formed between the source and drain regions. A gate and gate oxide are formed on the channel and lightly doped source and drain extension regions are formed in the channel. The lightly doped source and drain regions extend across the channel from the source and the drain regions, respectively, occupying a substantial portion of the channel. Programming of the anti-fuse is performed by application of power to the gate and at least one of the source region and the drain region to break-down the gate oxide, which minimizes resistance between the gate and the channel.Type: GrantFiled: February 9, 2004Date of Patent: June 7, 2005Assignee: Broadcom CorporationInventors: Akira Ito, Douglas D. Smith, Myron J. Buer
-
Publication number: 20040157379Abstract: An anti-fuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A channel is formed between the source and drain regions. A gate and gate oxide are formed on the channel and lightly doped source and drain extension regions are formed in the channel. The lightly doped source and drain regions extend across the channel from the source and the drain regions, respectively, occupying a substantial portion of the channel. Programming of the anti-fuse is performed by application of power to the gate and at least one of the source region and the drain region to break-down the gate oxide, which minimizes resistance between the gate and the channel.Type: ApplicationFiled: February 9, 2004Publication date: August 12, 2004Applicant: Broadcom CorporationInventors: Akira Ito, Douglas D. Smith, Myron J. Buer
-
Publication number: 20040156224Abstract: The present invention relates to a method and circuit for verifying the state of a gated fuse element used with a one-time programmable CMOS memory device. A first expected state is set and a state of a first gate-ox fuse is sensed. The state of the first gate-ox fuse is compared to the first expected state to determine if they are equal, and a first signal is generated. A second expected state is set and a state of a second gate-ox fuse is sensed. The state of the second gate-ox fuse is compared to the second expected state to determine if they are equal, and a second signal is generated. A valid output is generated if both the first and second signals are in a correct state, both signals are high for example.Type: ApplicationFiled: January 14, 2004Publication date: August 12, 2004Inventors: Myron J. Buer, Douglas D. Smith
-
Patent number: 6704236Abstract: A method and circuit for verifying the state of a gated fuse element used with a one-time programmable CMOS memory device. A first expected state is set and a state of a first gate-ox fuse is sensed. The state of the first gate-ox fuse is compared to the first expected state to determine if they are equal, and a first signal is generated. A second expected state is set and a state of a second gate-ox fuse is sensed. The state of the second gate-ox fuse is compared to the second expected state to determine if they are equal, and a second signal is generated. A valid output is generated if both the first and second signals are in a correct state, both signals are high for example.Type: GrantFiled: January 3, 2002Date of Patent: March 9, 2004Assignee: Broadcom CorporationInventors: Myron J. Buer, Douglas D. Smith
-
Patent number: 6700176Abstract: An anti-fuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A channel is formed between the source and drain regions. A gate and gate oxide are formed on the channel and lightly doped source and drain extension regions are formed in the channel. The lightly doped source and drain regions extend across the channel from the source and the drain regions, respectively, occupying a substantial portion of the channel. Programming of the anti-fuse is performed by application of power to the gate and at least one of the source region and the drain region to break-down the gate oxide, which minimizes resistance between the gate and the channel.Type: GrantFiled: July 18, 2002Date of Patent: March 2, 2004Assignee: Broadcom CorporationInventors: Akira Ito, Douglas D. Smith, Myron J. Buer
-
Publication number: 20040023440Abstract: An anti-fuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A channel is formed between the source and drain regions. A gate and gate oxide are formed on the channel and lightly doped source and drain extension regions are formed in the channel. The lightly doped source and drain regions extend across the channel from the source and the drain regions, respectively, occupying a substantial portion of the channel. Programming of the anti-fuse is performed by application of power to the gate and at least one of the source region and the drain region to break-down the gate oxide, which minimizes resistance between the gate and the channel.Type: ApplicationFiled: July 18, 2002Publication date: February 5, 2004Applicant: Broadcom CorporationInventors: Akira Ito, Douglas D. Smith, Myron J. Buer
-
Publication number: 20030123314Abstract: The present invention relates to a method and circuit for verifying the state of a gated fuse element used with a one-time programmable CMOS memory device. A first expected state is set and a state of a first gate-ox fuse is sensed. The state of the first gate-ox fuse is compared to the first expected state to determine if they are equal, and a first signal is generated. A second expected state is set and a state of a second gate-ox fuse is sensed. The state of the second gate-ox fuse is compared to the second expected state to determine if they are equal, and a second signal is generated. A valid output is generated if both the first and second signals are in a correct state, both signals are high for example.Type: ApplicationFiled: January 3, 2002Publication date: July 3, 2003Inventors: Myron J. Buer, Douglas D. Smith
-
Patent number: 6442061Abstract: A method of forming a memory cell according to the present invention. A first pass gate transistor is formed of a first transistor type. The first pass gate transistor has a gate oxide with a first thickness. The source of the first pass gate transistor is electrically connected to a first bit line, and the drain of the first pass gate transistor is electrically connected to a first state node. The gate of the first pass gate transistor is electrically connected to a memory cell enable line. A second pass gate transistor is also formed of the first transistor type. The second pass gate transistor also has a gate oxide with the first thickness. The source of the second pass gate transistor is electrically connected to a second bit line, and the drain of the second pass gate transistor is electrically connected to a second state node. The gate of the second pass gate transistor is electrically connected to the memory cell enable line. A first state node transistor is also formed of the first transistor type.Type: GrantFiled: February 14, 2001Date of Patent: August 27, 2002Assignee: LSI Logic CorporationInventors: Weiran Kong, Gary K. Giust, Ramnath Venkatraman, Yauh-Ching Liu, Franklin Duan, Ruggero Castagnetti, Steven M. Peterson, Myron J. Buer, Minh Tien Nguyen