Abstract: This document discusses, among other things, circuits and methods for providing an indication of an impedance between a detecting pin and a first signal pin of an audio socket using first and second comparators to, among other things, determine if moisture is present in the audio socket. If moisture is present in the audio socket, communication between an audio processing unit and the audio socket can be disabled.

Abstract: This document discusses, among other things, an attack detection module configured to permanently shut down a slave device after a number of consecutive attacks.

Abstract: This document discusses, among other things, circuits and methods for providing an indication of an impedance between a detecting pin and a first signal pin of an audio socket using first and second comparators to, among other things, determine if moisture is present in the audio socket. If moisture is present in the audio socket, communication between an audio processing unit and the audio socket can be disabled.

Abstract: This document discusses, among other things, systems and methods to provide an internal supply rail with over voltage protection using a host power source, an external power source, and a switch configured to receive indications of host and external power source validity. In an example, the switch can be configured to provide the internal supply rail using the host power source when the indication of host power source validity indicates a valid host power source and the external power source when the indication of host power source validity indicates an invalid host power source and the indication of external power source validity indicates a valid external power source.

Abstract: This document discusses, among other things, a method of distributing authentication keys that can prevent certain forms of circuit fabrication piracy. In an example, a method can include selecting a number of authentication keys for generation at a key generation computer, generating a random number using a random number generator of the key generation computer, generating the number of authentication keys using the random number and a key generation algorithm stored in the memory of the key generation computer, scrambling each of the number of authentication keys using a scrambling routine executing on the key generation computer, and distributing the scrambled authentication keys to an authorized manufacturers.

Abstract: This document discusses, among other things, an attack detection module configured to permanently shut down a slave device after a number of consecutive attacks.

Abstract: This document discusses, among other things, systems and methods to provide an internal supply rail with over voltage protection using a host power source, an external power source, and a switch configured to receive indications of host and external power source validity. In an example, the switch can be configured to provide the internal supply rail using the host power source when the indication of host power source validity indicates a valid host power source and the external power source when the indication of host power source validity indicates an invalid host power source and the indication of external power source validity indicates a valid external power source.

Abstract: An ESD protection circuit is described that protects the output transistors of a target circuit, usually an integrated circuit, that has an output enable, OE, or similar control input. An OE signal turns off the output transistors allowing the target circuit output, or outputs, to electrically float. Such a condition is commonly called a three state condition. The inventive protection circuit is not connected to the output directly, it senses an ESD voltage spike at the +Vdd contact to the circuit and produces a timed signal. The timed signal is converted to logic levels and gated with the OE signal (that the system previously provided to the OE control input). The output of gate forms a new OE control input signal that forces the target circuit into its three state condition during the period of the timed signal.

Abstract: This document discusses, among other things, systems and methods to provide an internal supply rail with over voltage protection using a host power source, an external power source, and a switch configured to receive indications of host and external power source validity. In an example, the switch can be configured to provide the internal supply rail using the host power source when the indication of host power source validity indicates a valid host power source and the external power source when the indication of host power source validity indicates an invalid host power source and the indication of external power source validity indicates a valid external power source.

Abstract: An FET switch comprising a single or parallel opposite polarity FETS is illustrated with wells that are driven from internal power rails. The internal power rails are logically coupled by other driving FET switches to, in one case, the higher of a positive power supply or signal level wherein the well of the PMOS FET switch will not allow the drain/source to well diode to be forward biased. In a second case, a second power rail is logically coupled to the lower of either and input signal or ground, wherein the well of the NMOS FET will not allow the drain/source to well diode to be forward biased.

Abstract: A pass-gate having a single or parallel opposite polarity FETs is disclosed. The wells of the primary transistor switches are driven from circuitry that reduces over-voltage leakage and other malfunctions. A circuit that drives the wells is also used to power enable circuits that drive the gates of the pass transistors. The use of separate circuits to the gate and the wells further reduces leakage. In the condition of power supply voltage and signal levels that are near the thresholds of the FETs involved, one or more Schottky diodes may be used across pn junctions in the FETs that will prevent turning on the pn junctions.

Abstract: A pass-gate having a single or parallel opposite polarity FETs is disclosed. The wells of the primary transistor switches are driven from circuitry that reduces over-voltage leakage and other malfunctions. A circuit that drives the wells is also used to power enable circuits that drive the gates of the pass transistors. The use of separate circuits to the gate and the wells further reduces leakage. In the condition of power supply voltage and signal levels that are near the thresholds of the FETs involved, one or more Schottky diodes may be used across pn junctions in the FETs that will prevent turning on the pn junctions.

Abstract: An FET switch comprising a single or parallel opposite polarity FETS is illustrated with wells that are driven from internal power rails. The internal power rails are logically coupled by other driving FET switches to, in one case, the higher of a positive power supply or signal level wherein the well of the PMOS FET switch will not allow the drain/source to well diode to be forward biased. In a second case, a second power rail is logically coupled to the lower of either and input signal or ground, wherein the well of the NMOS FET will not allow the drain/source to well diode to be forward biased.

Abstract: A DC symmetrical FET switch includes second and third switches connecting the well of the symmetrical FET switch to the drains and the source when the symmetrical FET switch is on. When the three FET's are on, the well, source and drain of the symmetric FET switch all exhibit the same input signal, wherein the drains and source to well capacitances are substantially prevented from draining off any of the input signal, thereby increasing the bandwidth and decreasing the insertion loss of the switch. The second and third switches are also FET switches. An enable signal is connected to the gates of all three FET's turning them on and off together. When the enable is false the FET switches are turned off and their wells are driven to a potential a proper potential. When the FET's are n-type the potential is low and when the FET's are p-types the potential is high.

Abstract: A bus hold circuit of CMOS components that draws no DC current and is over voltage tolerant is described. No leakage current is drawn from the input when the input voltage is greater than the bus hold circuit supply voltage. A feedback inverter is used to s latch the Vin logic in the bus hold circuit. When Vin is low, it turns on a first switch that drives the gate of a PMOS switch low turning it on. The PMOS switch connects the power connection of the feedback inverter to Vcc. The gate remains low, keeping the PMOS switch turned on as Vin increases. The first switch is turned off, but the gate of the PMOS switch remains low, until Vin exceeds Vcc. At that point, a comparator drives the gate of the PMOS to Vin shutting the PMOS switch off. An arbiter circuit selects the higher of Vcc and Vin to bias the N-well of the PMOS switch and other PMOS components in the comparator and arbiter circuit. This biasing ensures that the N-wells are never forward biased, thereby preventing leakage from the Vin.

Abstract: A circuit using current starved pull up and pull down transistors is arranged to connect a current source via each transistors to an output transistor stage. The current source values are selected so that the starved transistors provide a known voltage edge rate profile as a function of the current sources and the parameters of the transistors. Two or more additional current sources, that when enabled contribute current in parallel with the first current sources such that controlled edge rate profiles are selectively speeded up in response the enabled current sources. An enable input is provided for each additional current source for selectably controlling the faster or slower edge rate profiles. Reference voltages are used to determine the current source values along with transistor parameters. Preferably the transistor are MOSFETs.

Abstract: A bus switch for transferring logic signals between nodes without the problems associated with undershoot conduction. The bus switch is an FET switch including a single primary transfer transistor. The bulk of the transfer transistor is coupled to a differential logic sense circuit that is designed to establish a pseudo low-potential power rail. The logic sense circuit is coupled to the two transfer nodes and a standard low-potential power rail. It compares the potentials associated with the transfer node signals and the low-potential rail and selects the one with the lowest potential to establish the potential of the pseudo low-potential rail. The logic sense circuit provides for active selection of the lowest potential element, including under very small undershoot conditions.

Abstract: A bus switch for transferring logic signals between nodes without the problems associated with undershoot conduction. The bus switch is an FET switch including a single primary transfer transistor. The bulk of the transfer transistor is coupled to a bulk regulating circuit including a pseudo low-potential power rail. The pseudo low-potential rail is coupled to one arbiter circuit associated with one of the two circuit transfer nodes and a second arbiter circuit associated with the other of the two transfer nodes. The arbiter circuits are coupled to their respective nodes or pads and to a common low-potential supply rail. The arbiter selects for coupling to the pseudo low-potential rail the signal of the lower potential between that at the pad and that of the low-potential rail. This arrangement ensures that there will be no parasitic conduction of the transfer transistor during undershoot conditions.

Abstract: A wafer structure and a method of fabricating and testing IC dies (10) on a wafer (12) are incorporated in a wafer fabrication process which produces IC dies having a selected sensitive AC parameter (L.sub.EFF,.beta.,R). Performance of the sensitive AC parameter generally falls within a first range of variation characteristic of the wafer fabrication process. A test structure or test pattern (TNMOS, TPMOS, TNPN, TR) is formed on substantially every die (10) of the wafer (12) for testing in a DC parametric test at the wafer level sorting stage before scribing and packaging the dies from the wafer. The test structures are constructed for generating test measurements in a DC parameter test reflecting the AC performance of the selected sensitive AC parameter. Substantially every die on the wafer is tested at the wafer level sorting stage using the test structures (TNMOS, TPMOS, TNPN, TR) in a DC parametric test. Those dies of the wafer reflecting AC performance of the selected sensitive AC parameter (L.sub.EFF, .

Abstract: This document discusses, among other things, systems and methods to provide an internal supply rail with over voltage protection using a host power source, an external power source, and a switch configured to receive indications of host and external power source validity. In an example, the switch can be configured to provide the internal supply rail using the host power source when the indication of host power source validity indicates a valid host power source and the external power source when the indication of host power source validity indicates an invalid host power source and the indication of external power source validity indicates a valid external power source.