Abstract: Methods and apparatus for scalable MCTP infrastructure. A system is split into independent MCTP domains, wherein each MCTP domain uses Endpoint Identifiers (EIDs) for endpoint devices within the MCTP domain in a manner similar to conventional MCTP operations. A new class of MCTP devices (referred to as a Domain Controllers) is provided to enable inter-domain communication and communication with global devices. Global traffic originators or receivers like a BMC (Baseboard Management Controller), Infrastructure Processing Unit (IPU), Smart NIC (Network Interface Card), Debugger, or PROT (Platform Root or Trust) discover and establish two-way communication through the Domain Controllers to any of the devices in the target domain(s). The Domain Controllers are configured to implement tunneled connections between global devices and domain endpoint devices.

Abstract: Methods and apparatus for scalable MCTP infrastructure. A system is split into independent MCTP domains, wherein each MCTP domain uses Endpoint Identifiers (EIDs) for endpoint devices within the MCTP domain in a manner similar to conventional MCTP operations. A new class of MCTP devices (referred to as a Domain Controllers) is provided to enable inter-domain communication and communication with global devices. Global traffic originators or receivers like a BMC (Baseboard Management Controller), Infrastructure Processing Unit (IPU), Smart NIC (Network Interface Card), Debugger, or PROT (Platform Root or Trust) discover and establish two-way communication through the Domain Controllers to any of the devices in the target domain(s). The Domain Controllers are configured to implement tunneled connections between global devices and domain endpoint devices.

Abstract: An apparatus and method to monitor status of a serial data signal on a low speed serial bus is provided. A controller configures a watchdog timer in each target device, sends a heart-beat command to all of the target devices over the low speed serial bus prior to the expiration of the watchdog timer and issues a broadcast read command to any one of the target devices on the low speed serial bus. A response to the broadcast read command confirms that the low speed serial bus is functional. If a response is not received, the low speed serial bus is not functional and the controller initiates a broadcast reset command to initialize all target devices on the low speed serial bus.

Abstract: Examples described herein relate to circuitry that is to manage communications to and from a manageability controller. In some examples, during communications on a first port, circuitry generates a bus busy condition for one or more other ports to block transactions from one or more devices.

Abstract: In one embodiment, an apparatus includes: a peer-to-peer (P2P) control circuit to issue a P2P communication request to a bus master of a multi-drop interconnect to request authorization to send a P2P transaction to at least one slave device coupled to the multi-drop interconnect; a transmitter to transmit the P2P transaction to the at least one slave device when the bus master grants the authorization for the P2P transaction; and another transmitter to output the clock signal to the multi-drop interconnect during the P2P transaction. Other embodiments are described and claimed.

Abstract: An apparatus may include a controller for a system management bus. The controller may be to: detect a trigger event associated with the system management bus; in response to a detection of the trigger event, transmit a broadcast address on the system management bus, where the broadcast address is not used in a first communication protocol; and in response to a determination that the transmitted broadcast address was acknowledged, use a second communication protocol for transmissions on the system management bus. Other embodiments are described and claimed.

Abstract: Embodiments of the present disclosure may relate to apparatus, process, or techniques in a I3C protocol environment that include identifying a pending read notification message by a slave device to be sent to a master device to indicate that the data is available to be read by the master device from a buffer associated with the slave device. The pending read notification may be subsequently transmitted to the master device. Subsequently, until the data in the buffer has been read by the master device, the slave device may wait an identified amount of time that is less than a value of a timeout of the master device, and retransmit the pending read notification message to the master device. Other embodiments may be described and/or claimed.

Abstract: Examples include techniques for implementing a write transaction to two or more memory devices in a storage device. In some examples, the write transaction includes an atomic write transaction from an application or operating system executing on a computing platform to a storage device coupled with the computing platform. For these examples, the storage device includes a storage controller to receive an atomic multimedia write transaction request to write first data and second data; cause the first data to be stored in a first memory device, and cause the second data to be stored in a second memory device, simultaneously and atomically.

Abstract: An embodiment of a semiconductor apparatus may include technology to determine a persistent region and a non-persistent region of a volatile media based on an amount of power available from one or more backup power sources, and periodically backup only the non-persistent region of the volatile media to a non-volatile media. Other embodiments are disclosed and claimed.

Abstract: An embodiment of a mass storage apparatus may include first non-volatile media, second non-volatile media which provides a relatively larger write granularity as compared to the first non-volatile media, and logic communicatively coupled to the first and second non-volatile media to direct an access request to one of the first non-volatile media and the second non-volatile media based on an indication from an operating system. An embodiment of a host computing apparatus may include a processor, memory communicatively coupled to the processor, and logic communicatively coupled to the processor to provide an indication for a file system-related access request to a mass storage device based on a granularity size for the file system-related access request. Other embodiments are disclosed and claimed.

Abstract: Techniques and mechanisms for exchanging information between a solid state drive (SSD) and a write-in-place non-volatile memory via a host device. In an embodiment, access control information defines state of the SSD, where the access control information determines and/or is based on an access by the host device to other non-volatile memory of the SSD. The access control information includes address conversion information defining a correspondence of a logical address with a physical address for a location of the other non-volatile memory of the SSD. At least some of the access control information is stored by the SSD to the write-in-place non-volatile memory for later retrieval by the SSD. In another embodiment, the SSD signals that a commit operation is to be performed to flush any cached or buffered access control information into the write-in-place non-volatile memory.

Abstract: In one embodiment, an apparatus includes: a peer-to-peer (P2P) control circuit to issue a P2P communication request to a bus master of a multi-drop interconnect to request authorization to send a P2P transaction to at least one slave device coupled to the multi-drop interconnect; a transmitter to transmit the P2P transaction to the at least one slave device when the bus master grants the authorization for the P2P transaction; and another transmitter to output the clock signal to the multi-drop interconnect during the P2P transaction. Other embodiments are described and claimed.

Abstract: An embodiment of a semiconductor package apparatus may include technology to determine prior state information corresponding to one or more of a power state, a system state, a device state, and an operating system state, and load an indirection structure for a persistent storage media in the background based on the prior state information. Other embodiments are disclosed and claimed.

Abstract: An embodiment of a mass storage apparatus may include first non-volatile media, second non-volatile media which provides a relatively larger write granularity as compared to the first non-volatile media, and logic communicatively coupled to the first and second non-volatile media to direct an access request to one of the first non-volatile media and the second non-volatile media based on an indication from an operating system. An embodiment of a host computing apparatus may include a processor, memory communicatively coupled to the processor, and logic communicatively coupled to the processor to provide an indication for a file system-related access request to a mass storage device based on a granularity size for the file system-related access request. Other embodiments are disclosed and claimed.

Abstract: An embodiment of a semiconductor package apparatus may include technology to determine prior state information corresponding to one or more of a power state, a system state, a device state, and an operating system state, and load an indirection structure for a persistent storage media in the background based on the prior state information. Other embodiments are disclosed and claimed.

Abstract: An embodiment of a semiconductor apparatus may include technology to determine a persistent region and a non-persistent region of a volatile media based on an amount of power available from one or more backup power sources, and periodically backup only the non-persistent region of the volatile media to a non-volatile media. Other embodiments are disclosed and claimed.

Abstract: Examples include techniques for implementing a write transaction to two or more memory devices in a storage device. In some examples, the write transaction includes an atomic write transaction from an application or operating system executing on a computing platform to a storage device coupled with the computing platform. For these examples, the storage device includes a storage controller to receive an atomic multimedia write transaction request to write first data and second data; cause the first data to be stored in a first memory device, and cause the second data to be stored in a second memory device, simultaneously and atomically.

Abstract: A mass storage device controller is described. The controller is to process first and second read requests received at an I/O interface of a mass storage device. The first read request includes a first logical block address. The first read request is to provide a first block stored within non volatile storage media of the mass storage device at the I/O interface. The first block is identified by the first logical block address. The second read request includes a second logical block address and specifies one or more bytes within a second block identified by the second block address and stored within the non volatile storage media. The second read request is to provide the one or more bytes at the I/O interface.

Abstract: Methods, apparatus, systems and articles of manufacture to preserve data of a solid state drive during a power loss event are disclosed. An example method includes setting an alternate data cache (PDC1) to a logical AND of a secondary data cache (SDC) and a primary data cache (PDC0). The PDC1 is set to a logical AND of the PDC1 and a first result of a first sense operation. The PDC0 is set to a logical AND of the PDC0 and an inverse value of the PDC1. The PDC1 is set to a logical AND of the SDC and the PDC0. The PDC1 is set to a logical AND of the PDC1 and an inverse value of a second result of a second sense operation. The SDC is set to a logical AND of the SDC and the PDC0. The SDC is set to a logical OR of the SDC or the PDC0. The PDC0 is set to a logical AND of the PDC0 and a third result of a third sensing operation.

Abstract: Methods, apparatus, systems and articles of manufacture to preserve data of a solid state drive during a power loss event are disclosed. An example method includes setting an alternate data cache (PDC1) to a logical AND of a secondary data cache (SDC) and a primary data cache (PDC0). The PDC1 is set to a logical AND of the PDC1 and a first result of a first sense operation. The PDC0 is set to a logical AND of the PDC0 and an inverse value of the PDC1. The PDC1 is set to a logical AND of the SDC and the PDC0. The PDC1 is set to a logical AND of the PDC1 and an inverse value of a second result of a second sense operation. The SDC is set to a logical AND of the SDC and the PDC0. The SDC is set to a logical OR of the SDC or the PDC0. The PDC0 is set to a logical AND of the PDC0 and a third result of a third sensing operation.