Abstract: A router may include input buffers that receive a packet being transmitted from a source to a destination, a state generator that determines a state for the packet, and a memory representing weights for actions corresponding to possible states. The memory may be configured to return an action corresponding to the state of the packet, where the action may indicate a next hop in the route between the source and the destination. The router may also include reward logic configured to generate the weights for the plurality of actions in the memory. The reward logic may receive a global reward corresponding to the route between the source and the destination, calculate a local reward corresponding to next hops available to the router; and combine the global reward and the local reward to generate the weights for the plurality of actions in the memory.

Abstract: A method of inducing sparsity for outputs of neural network layer may include receiving outputs from a layer of a neural network; partitioning the outputs into a plurality of partitions; identifying first partitions in the plurality of partitions that can be treated as having zero values; generating an encoding that identifies locations of the first partitions among remaining second partitions in the plurality of partitions; and sending the encoding and the second partitions to a subsequent layer in the neural network.

Abstract: A network-on-package (NoPK) for connecting a plurality of chiplets may include a plurality of interface bridges configured to convert a plurality of protocols used by the plurality of chiplets into a common protocol, a routing network configured to route traffic between the plurality of interface bridges using the common protocol, and a controller configured to program the plurality of interface bridges and the routing network based on types of the plurality of chiplets connected to the NoPK. The NoPK may provide a scalable connection for any number of chiplets from different ecosystems using different communication protocols.

Abstract: A network-on-package (NoPK) for connecting a plurality of chiplets may include a plurality of interface bridges configured to convert a plurality of protocols used by the plurality of chiplets into a common protocol, a routing network configured to route traffic between the plurality of interface bridges using the common protocol, and a controller configured to program the plurality of interface bridges and the routing network based on types of the plurality of chiplets connected to the NoPK. The NoPK may provide a scalable connection for any number of chiplets from different ecosystems using different communication protocols.

Abstract: A system and method for reducing active power in processors is disclosed. A method embodiment comprises the steps of determining when a particular logic block is inactive, determining the powered state of the particular logic block, isolating the particular logic block from a main processor core, and powering off the particular logic block. When the system needs the particular logic block, the method further comprises reactivating the block. A system embodiment comprises software and a processor coupled to a clock control module, an isolation control module and a header/footer module, operable to isolate a particular logic block and power off a particular logic block, thereby reducing power. Another embodiment comprises a logic module coupled to a clock by a clock gating module, an isolation module for isolating the logic module, a header/footer module for disabling power to the logic module, and a power and clock gating control module for controlling the clock gating module and the header/footer module.

Abstract: A system and method for reducing active power in processors is disclosed. A method embodiment comprises the steps of determining when a particular logic block is inactive, determining the powered state of the particular logic block, isolating the particular logic block from a main processor core, and powering off the particular logic block. When the system needs the particular logic block, the method further comprises reactivating the block. A system embodiment comprises software and a processor coupled to a clock control module, an isolation control module and a header/footer module, operable to isolate a particular logic block and power off a particular logic block, thereby reducing power. Another embodiment comprises a logic module coupled to a clock by a clock gating module, an isolation module for isolating the logic module, a header/footer module for disabling power to the logic module, and a power and clock gating control module for controlling the clock gating module and the header/footer module.

Abstract: A method and apparatus for emulating the intermediate 16-bit truncation of the address in the 8086 architecture using a 32-bit adder. The preferred embodiment of the invention adds the displacement, base address, and segment base values in a three-port carry save adder. The displacement value and base address are also added together in a two-port full adder. The outputs of the three-port carry save adder and two-port full adder are then compared to determine whether a carry from bit 16, if any, resulted from the addition of the displacement and base address value or the addition of the segment base value. A logic unit determines whether a carry into bit position 16 of the linear address is modified. If the carry is the result of the addition of the segment base value to the effective address, the carry is not modified. If the carry is the result of the addition of the base and displacement value, the carry is modified by forcing the bit position 16 to zero.