Abstract: The invention provides a high-speed buffer that may used at the input of an integrated circuit, such as an input buffer. This buffer may be configured for use as a standard buffer with a single switching threshold, such as a TTL-to-CMOS buffer, or used as a Schmitt trigger with hysteresis, which as at least two switching thresholds. The integrated circuit may be a programmable logic device (PLD) or field programmable gate array (FPGA), but in other embodiments, the integrated circuit may be other types of devices such a microprocessors, ASICs, or memories.

Abstract: Disclosed is a method and apparatus for evaluating margin voltages in single poly EEPROM cells. Briefly, the invention involves shifting the cell's threshold voltage higher, resulting in a corresponding rise in the margin voltage, so that testing for the erase margin may be conducted in the positive voltage range. The present invention implements a variety of solutions to the problem, including both innovations in cell processing and circuitry. In one embodiment, the process steps employed to create the floating gate transistor are changed in order to increase its threshold voltage. Alternatively, or in combination with these general process changes, the width of the floating gate transistor may be reduced, resulting in a corresponding increase in the margin voltage.

Abstract: A charge pump circuit is described. The charge pump circuit includes: a first pumping stage, where the first pumping stage receives a first input voltage and a second input voltage and outputs a first output voltage and a second output voltage, and at least a second pumping stage coupled to the first pumping stage, where the second pumping stage receives the first output voltage and the second output voltage and outputs at least a third output voltage, further where the first output voltage and the second output voltage are output within one clock cycle.

Abstract: Disclosed is a method and apparatus for evaluating margin voltages in single poly EEPROM cells. Briefly, the invention involves shifting the cell's threshold voltage higher, resulting in a corresponding rise in the margin voltage, so that testing for the erase margin may be conducted in the positive voltage range. The present invention implements a variety of solutions to the problem, including both innovations in cell processing and circuitry. In one embodiment, the process steps employed to create the floating gate transistor are changed in order to increase its threshold voltage. Alternatively, or in combination with these general process changes, the width of the floating gate transistor may be reduced, resulting in a corresponding increase in the margin voltage.

Abstract: A programmable input/output circuit for a programmable logic device input/output pin can be configured in a standard I/O mode, or in a reference voltage mode. The circuit includes a tristatable, but otherwise standard I/O buffer as well as a reference voltage clamp circuit. In reference voltage mode, the I/O circuit is tristated, and the reference voltage clamp circuit passes a reference voltage from the I/O pin to a reference voltage bus. In standard I/O mode, the I/O buffer is operational. The reference voltage clamp circuit isolates the I/O pin from the reference voltage bus and may include undervoltage and overvoltage protection to prevent disturbance of the reference voltage bus by an out-of-range I/O signal.

Abstract: A programmable input/output circuit for a programmable logic device input/output pin can be configured in a standard I/O mode, or in a reference voltage mode. The circuit includes a tristatable, but otherwise standard I/O buffer as well as a reference voltage clamp circuit. In reference voltage mode, the I/O circuit is tristated, and the reference voltage clamp circuit passes a reference voltage from the I/O pin to a reference voltage bus. In standard I/O mode, the I/O buffer is operational. The reference voltage clamp circuit isolates the I/O pin from the reference voltage bus and may include undervoltage and overvoltage protection to prevent disturbance of the reference voltage bus by an out-of-range I/O signal.

Abstract: Disclosed is a method and apparatus for evaluating margin voltages in single poly EEPROM cells. Briefly, the invention involves shifting the cell's threshold voltage higher, resulting in a corresponding rise in the margin voltage, so that testing for the erase margin may be conducted in the positive voltage range. The present invention implements a variety of solutions to the problem, including both innovations in cell processing and circuitry. In one embodiment, the process steps employed to create the floating gate transistor are changed in order to increase its threshold voltage. Alternatively, or in combination with these general process changes, the width of the floating gate transistor may be reduced, resulting in a corresponding increase in the margin voltage.

Abstract: An integrated circuit contains circuitry to operate in such a fashion to reduce output noise when switching output circuits from a programming mode to a user mode. In an implementation, the integrated circuit (125) is configurable in the programming mode with user configuration data. In the user mode, the integrated circuit will operate with the functionality as defined by the user during the programming mode. When switching from the programming mode to the user mode, each output (210) of the integrated circuit will switch to its user mode value. In order to minimize switching noise, the outputs are released to their user mode values not all at the same time.

Abstract: An output buffer with feedback to a predriver circuit such that the effective size of the predriver buffers are momentarily adjusted to favor a particular transition (i.e., low-to-high or high-to-low). The delayed output selectively alters the input threshold characteristic of the predriver circuit to favor the appropriate transition. Thus, the time during which the output drivers are subject to a crowbar current is reduced over previous devices.

Abstract: An output buffer comprising control circuit for reducing the amount of ground and/or power bounce noise. The output buffer further includes one or more driver devices. The output current of the driver device(s) is limited by providing an intermediate drive voltage to the control electrode of the driver device. A pass device (or a transmission gate) provides the intermediate drive voltage and also operates as a variable resistive device that limits the slew rate of the drive voltage. The operation of the pass device can be dependent on a signal level at the output of the output buffer. When the output has transitioned to a new logic state, the new logic level is fed back to change the operating state of the pass device, thus ensuring that the output voltage meets the output VOL and VOH specifications.

Abstract: A power supply independent voltage reference circuit is disclosed. According to the invention a reference voltage is generated at a common node between a pull-up transistor that is biased by a power supply dependent bias voltage, and a pull-down transistor that is biased by a feedback signal based on the output voltage level.

Abstract: Various embodiments for controlling a ramp rate of a high voltage generator circuit such as a charge pump circuit are disclosed. In one embodiment the ramp rate of the output signal is controlled by modulating an amplitude of the oscillating signal at the input of the charge pump circuit. In another embodiment, the ramp rate is controlled by modulating the current loading at the output of the charge pump circuit. In yet another embodiment, the ramp rate of the output signal is controlled by modulating the frequency of the oscillating signal at the input of the charge pump circuit.

Abstract: Disclosed is a method for biasing dual row line EEPROM cells. The new biasing scheme improves the data retention lifetime of an EEPROM cell by reducing the potential difference between the control gate and the write column of the cell, which reduces the tunnel oxide electric field. In a preferred embodiment, the method involves applying bias voltages to the control gate and write column of an EEPROM cell such that the potential difference between the control gate and the right column is no more than about 0.5 volts. By biasing the cell's write column to a positive voltage, the tunnel oxide field may be significantly reduced. Moreover, the invention provides a method of selecting a write column voltage based on a control gate voltage such that the tunnel oxide field is substantially balanced in all its modes. This biasing scheme minimizes SILC and improves cell reliability.

Abstract: The present invention is a sense amplifier circuit for use with programmable logic devices that provides improved switching time by actively limiting the voltage swing on the bit line which it is sensing, rather than passively sensing the voltage, employs feedback circuits to further improve switching time and may be selectively operated in low power mode without significant reduction in switching speed. Voltage reference control circuitry, comprising variable current limiters controlled by the potential of a supply of reference potential, can be added to improve noise immunity. The circuitry of the supply of reference potential is designed so that its sensitivity to fabrication variations is substantially similar to that of the sense amplifier and so that it adjusts the reference potential accordingly.

Abstract: A high voltage pump with an initiation scheme to achieve voltages above VDD. In response to a pulse signal, an initiation voltage is placed on a first node (515) of a voltage pump to initiate pumping action. The initiation voltage is passed through a transistor (545) coupled between a high voltage output node (415) and the first node (515) of the voltage pump. The first node (515) is coupled through a capacitor (510) to an oscillator (405) which charges the first node (515). A high voltage is produced at the high voltage output node (415). The initiation scheme may be applied to one-stage and multiple-stage voltage pumps.

Abstract: The present invention is a sense amplifier circuit for use with programmable logic devices, that provides improved switching time by actively limiting the voltage swing on the bit line which it is sensing, rather than passively sensing the voltage, and that employs feedback circuits to further improve switching time. Voltage reference control circuitry, comprising variable current limiters controlled by the potential of a supply of reference potential, can be added to improve noise immunity. The circuitry of the supply of reference potential is designed so that its sensitivity to fabrication variations is substantially similar to that of the sense amplifier and so that it adjusts the reference potential accordingly.

Abstract: An EPROM or EEPROM employs an alternate voltage level of 2 volts replaces solid ground (0 volts) during programming and performs a `zero` logic level function. This `soft` zero of 2 volts is applied to bit lines not selected for programming. As a soft zero, this alternative voltage reduces internal voltage stresses and helps prevent field inversion and keep parasitic field transistors between bit lines shut off. By reducing internal voltage stresses on gate oxides, and by helping prevent field inversion, the use of a soft zero voltage allows smaller circuit architectures to be designed for a given high programming voltage.

Abstract: A set of signal buffering circuits for driving heavily loaded signal lines. The buffer circuits detect a signal transition before the signal reaches logical threshold levels, and help drive the signal in the detected transition direction. The early transition detection and drive help reduce signal propagation delay across heavily loaded lines.

Abstract: A programmable logic device is provided that has a two-dimensional array of logic array blocks. The logic array blocks, which contain advanced macrocells, contain programmable input arrays based on pterm logic and are two-dimensionally interconnected with global horizontal and vertical conductors. The logic array blocks and the connections between conductors are configured using programmable multiplexers and demultiplexers. Redundant conductive pathways are provided so that the programmable logic device may be efficiently programmed to perform a variety of logic functions. Furthermore, logic is provided with each logic array block that allows the global horizontal and vertical conductors to be interconnected without directly involving the logic in the logic array block, which therefore can be used to provide greater logical functionality.

Abstract: A programmable logic device is provided that has redundant circuitry. When a portion of the programmable logic device circuitry is found to be defective, the redundant circuitry is switched into use in place of the defective circuitry by programming appropriate portions of the circuitry of the programmable logic device. The programmable logic device is arranged in rows and columns of programmable logic containing logic array blocks, which a user selectively configures by loading programming data into vertical and horizontal programming blocks. Programming blocks are used to program the logic array blocks and various associated logic circuitry. When the redundant circuitry is switched into place, the programming data is redirected to the appropriate programming blocks, so that the device functions identically, regardless of whether or not the redundant circuitry is used.