Patents by Inventor Mysore S. Srinivas

Mysore S. Srinivas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120096241
    Abstract: A method, system and computer-usable medium are disclosed for managing transient instruction streams. Transient flags are defined in Branch-and-Link (BRL) instructions that are known to be infrequently executed. A bit is likewise set in a Special Purpose Register (SPR) of the hardware (e.g., a core) that is executing an instruction request thread. Subsequent fetches or prefetches in the request thread are treated as transient and are not written to lower-level caches. If an instruction is non-transient, and if a lower-level cache is non-inclusive of the L1 instruction cache, a fetch or prefetch miss that is obtained from memory may be written in both the L1 and the lower-level cache. If it is not inclusive, a cast-out from the L1 instruction cache may be written in the lower-level cache.
    Type: Application
    Filed: October 15, 2010
    Publication date: April 19, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert H. Bell, JR., Hong L. Hua, Ram Raghavan, Mysore S. Srinivas
  • Publication number: 20120096240
    Abstract: A method, system and computer-usable medium are disclosed for managing prefetch streams in a virtual machine environment. Compiled application code in a first core, which comprises a Special Purpose Register (SPR) and a plurality of first prefetch engines, initiates a prefetch stream request. If the prefetch stream request cannot be initiated due to unavailability of a first prefetch engine, then an indicator bit indicating a Prefetch Stream Dispatch Fault is set in the SPR, causing a Hypervisor to interrupt the execution of the prefetch stream request. The Hypervisor then calls its associated operating system (OS), which determines prefetch engine availability for a second core comprising a plurality of second prefetch engines. If a second prefetch engine is available, then the OS migrates the prefetch stream request from the first core to the second core, where it is initiated on an available second prefetch engine.
    Type: Application
    Filed: October 15, 2010
    Publication date: April 19, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew Accapadi, Robert H. Bell, JR., Hong L. Hua, Ram Raghavan, Mysore S. Srinivas
  • Publication number: 20110320573
    Abstract: A method, apparatus, and computer program product for running software on an adapter. In response to a connection of a hardware interface for the adapter with a current host computer, a processor unit in the adapter determines whether a set of protocols for communicating with the current host computer to access resources is present on the adapter. In response to the set of protocols being absent on the adapter, the processor unit obtains the set of protocols from the current host computer. The processor unit identifies a set of available resources in the current host computer for use by the adapter using the set of protocols. The processor unit runs software stored on a set of storage devices in the adapter using the set of available resources identified for use by the adapter.
    Type: Application
    Filed: June 24, 2010
    Publication date: December 29, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Diane G. Flemming, William A. Maron, Mysore S. Srinivas, Basu Vaidyanathan
  • Publication number: 20110161979
    Abstract: Functionality is implemented to determine that a plurality of multi-core processing units of a system are configured in accordance with a plurality of operating performance modes. It is determined that a first of the plurality of operating performance modes satisfies a first performance criterion that corresponds to a first workload of a first logical partition of the system. Accordingly, the first logical partition is associated with a first set of the plurality of multi-core processing units that are configured in accordance with the first operating performance mode. It is determined that a second of the plurality of operating performance modes satisfies a second performance criterion that corresponds to a second workload of a second logical partition of the system. Accordingly, the second logical partition is associated with a second set of the plurality of multi-core processing units that are configured in accordance with the second operating performance mode.
    Type: Application
    Filed: December 31, 2009
    Publication date: June 30, 2011
    Applicant: International Business Machines Corporation
    Inventors: Diane G. Flemming, William A. Maron, Ram Raghavan, Satya Prakash Sharma, Mysore S. Srinivas
  • Publication number: 20110153931
    Abstract: A storage subsystem combining solid state drive (SSD) and hard disk drive (HDD) technologies provides low access latency and low complexity. Separate free lists are maintained for the SSD and the HDD and blocks of file system data are stored uniquely on either the SSD or the HDD. When a read access is made to the subsystem, if the data is present on the SSD, the data is returned, but if the block is present on the HDD, it is migrated to the SSD and the block on the HDD is returned to the HDD free list. On a write access, if the block is present in the either the SSD or HDD, the block is overwritten, but if the block is not present in the subsystem, the block is written to the HDD.
    Type: Application
    Filed: December 22, 2009
    Publication date: June 23, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert H. Bell, JR., Men-Chow Chiang, Hong L. Hua, Mysore S. Srinivas
  • Publication number: 20110145505
    Abstract: Mechanisms are provided, for implementation in a data processing system having at least one physical processor and at least one associated cache memory, for allocating cache resources of the at least one cache memory to virtual processors of the data processing system. The mechanisms identify a plurality of high priority virtual processors in the data processing system. The mechanisms further determine a percentage of cache lines of the at least one cache memory to be assigned to high priority virtual processors. Moreover, the mechanisms mark a portion of the cache lines in the at least one cache memory as being evictable by only high priority virtual processors based on the determined percentage of cache lines to be assigned to high priority virtual processors. The marked portion of the cache lines cannot be evicted by lower priority virtual processors having a priority lower than the high priority virtual processors.
    Type: Application
    Filed: December 15, 2009
    Publication date: June 16, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vaijayanthimala K. Anand, Diane G. Flemming, William A. Maron, Mysore S. Srinivas
  • Publication number: 20110093861
    Abstract: A data processing system includes physical computing resources that include a plurality of processors. The plurality of processors include a first processor having a first processor type and a second processor having a second processor type that is different than the first processor type. The data processing system also includes a resource manager to assign portions of the physical computing resources to be used when executing logical partitions. The resource manager is configured to assign a first portion of the physical computing resources to a logical partition, to determine characteristics of the logical partition, the characteristics including a memory footprint characteristic, to assign a second portion of the physical computing resources based on the characteristics of the logical partition, and to dispatch the logical partition to execute using the second portion of the physical computing resources.
    Type: Application
    Filed: October 21, 2009
    Publication date: April 21, 2011
    Applicant: International Business Machines Corporation
    Inventors: Diane G. Flemming, Octavian F. Herescu, William A. Maron, Mysore S. Srinivas
  • Publication number: 20100223622
    Abstract: In a NUMA-topology computer system that includes multiple nodes and multiple logical partitions, some of which may be dedicated and others of which are shared, NUMA optimizations are enabled in shared logical partitions. This is done by specifying a home node parameter in each virtual processor assigned to a logical partition. When a task is created by an operating system in a shared logical partition, a home node is assigned to the task, and the operating system attempts to assign the task to a virtual processor that has a home node that matches the home node for the task. The partition manager then attempts to assign virtual processors to their corresponding home nodes. If this can be done, NUMA optimizations may be performed without the risk of reducing the performance of the shared logical partition.
    Type: Application
    Filed: February 27, 2009
    Publication date: September 2, 2010
    Applicant: International Business Machines Corporation
    Inventors: Vaijayanthimala K. Anand, Mark R. Funk, Steven R. Kunkel, Mysore S. Srinivas, Randal C. Swanberg, Ronald D. Young
  • Patent number: 7698531
    Abstract: A system, method and computer-readable medium for balancing access among multiple logical partitions to the physical system resources of a computer system employing system virtualization. Each of the logical partitions is classified, initially during a startup period, in accordance with a level of allocated dispatch window utilization. Performance metrics of one or more of the physical system resources are determined in association with one or more of the logical partitions. The performance metrics determination is performed at a hardware level independent of programming interrupts. During a dispatch window in which a given set of the physical system resources are configured for allocation to one of the logical partitions, the given set of physical system resources are re-allocated to a replacement logical partition in accordance with the determined performance metrics associated with the replacement logical partition and the dispatch window utilization classification of the replacement logical partition.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: April 13, 2010
    Assignee: International Business Machines Corporation
    Inventors: Diane G. Flemming, Octavian F. Herescu, William A. Maron, Mysore S. Srinivas
  • Patent number: 7698530
    Abstract: A system, method and computer-readable medium for balancing access among multiple logical partitions to the physical system resources of a computer system employing system virtualization. Each of the logical partitions is classified, initially during a startup period, in accordance with a level of allocated dispatch window utilization. Performance metrics of one or more of the physical system resources are determined in association with one or more of the logical partitions. The performance metrics determination is performed at a hardware level independent of programming interrupts. During a dispatch window in which a given set of the physical system resources are configured for allocation to one of the logical partitions, the given set of physical system resources are re-allocated to a replacement logical partition in accordance with the determined performance metrics associated with the replacement logical partition and the dispatch window utilization classification of the replacement logical partition.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: April 13, 2010
    Assignee: International Business Machines Corporation
    Inventors: Diane G. Flemming, Octavian F. Herescu, William A. Maron, Mysore S. Srinivas
  • Patent number: 7640400
    Abstract: A method, computer program product, and system are provided for prefetching data into a cache memory. As a program is executed an object identifier is obtained of a first object of the program. A lookup operation is performed on a data structure to determine if the object identifier is present in the data structure. Responsive to the object identifier being present in the data structure, a referenced object identifier is retrieved that is referenced by the object identifier. Then, the data associated with the referenced object identifier is prefetched from main memory into the cache memory.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: December 29, 2009
    Assignee: International Business Machines Corporation
    Inventors: William A. Maron, Greg R. Mewhinney, Mysore S. Srinivas, David B. Whitworth
  • Patent number: 7617375
    Abstract: A system, method and computer-readable medium for balancing access among multiple logical partitions to the physical system resources of a computer system employing system virtualization. Each of the logical partitions is classified, initially during a startup period, in accordance with a level of allocated dispatch window utilization. Performance metrics of one or more of the physical system resources are determined in association with one or more of the logical partitions. The performance metrics determination is performed at a hardware level independent of programming interrupts. During a dispatch window in which a given set of the physical system resources are configured for allocation to one of the logical partitions, the given set of physical system resources are re-allocated to a replacement logical partition in accordance with the determined performance metrics associated with the replacement logical partition and the dispatch window utilization classification of the replacement logical partition.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: November 10, 2009
    Assignee: International Business Machines Corporation
    Inventors: Diane G. Flemming, Octavian F. Herescu, William A. Maron, Mysore S. Srinivas
  • Publication number: 20090252057
    Abstract: A method and system for replacing physical connections within a large enterprise system with wireless connections. A first wireless transceiver is associated with a node, wherein the node comprises one or more system service processors. A second wireless transceiver is associated with a main system service processor. System service processors associated with the node, referred to as node service processors, are assigned a unique identification (ID), e.g., a name and/or number, to identify the node service processors during wireless connection. An Ethernet cable is utilized to connect the node service processors to the main system service processor. The unique identification is transferred from the main system service processor to the node service processor, and then the Ethernet cable is disconnected. When the Ethernet cable is disconnected, the node service processor(s) communicate with the main system service processor via a wireless network utilizing the transceivers and unique IDs.
    Type: Application
    Filed: April 2, 2008
    Publication date: October 8, 2009
    Inventors: DIANE G. FLEMMING, Ghadir R. Gholami, Octavian F. Herescu, William A. Maron, Mysore S. Srinivas
  • Publication number: 20080256302
    Abstract: A method, computer program product, and system are provided for prefetching data into a cache memory. As a program is executed an object identifier is obtained of a first object of the program. A lookup operation is performed on a data structure to determine if the object identifier is present in the data structure. Responsive to the object identifier being present in the data structure, a referenced object identifier is retrieved that is referenced by the object identifier. Then, the data associated with the referenced object identifier is prefetched from main memory into the cache memory.
    Type: Application
    Filed: April 10, 2007
    Publication date: October 16, 2008
    Inventors: William A. Maron, Greg R. Mewhinney, Mysore S. Srinivas, David B. Whitworth
  • Publication number: 20080244214
    Abstract: A system, method and computer-readable medium for balancing access among multiple logical partitions to the physical system resources of a computer system employing system virtualization. Each of the logical partitions is classified, initially during a startup period, in accordance with a level of allocated dispatch window utilization. Performance metrics of one or more of the physical system resources are determined in association with one or more of the logical partitions. The performance metrics determination is performed at a hardware level independent of programming interrupts. During a dispatch window in which a given set of the physical system resources are configured for allocation to one of the logical partitions, the given set of physical system resources are re-allocated to a replacement logical partition in accordance with the determined performance metrics associated with the replacement logical partition and the dispatch window utilization classification of the replacement logical partition.
    Type: Application
    Filed: March 28, 2007
    Publication date: October 2, 2008
    Inventors: Diane G. Flemming, Octavian F. Herescu, William A. Maron, Mysore S. Srinivas
  • Publication number: 20080244215
    Abstract: A system, method and computer-readable medium for balancing access among multiple logical partitions to the physical system resources of a computer system employing system virtualization. Each of the logical partitions is classified, initially during a startup period, in accordance with a level of allocated dispatch window utilization. Performance metrics of one or more of the physical system resources are determined in association with one or more of the logical partitions. The performance metrics determination is performed at a hardware level independent of programming interrupts. During a dispatch window in which a given set of the physical system resources are configured for allocation to one of the logical partitions, the given set of physical system resources are re-allocated to a replacement logical partition in accordance with the determined performance metrics associated with the replacement logical partition and the dispatch window utilization classification of the replacement logical partition.
    Type: Application
    Filed: March 28, 2007
    Publication date: October 2, 2008
    Inventors: DIANE G. FLEMMING, Octavian F. Herescu, William A. Maron, Mysore S. Srinivas
  • Publication number: 20080244213
    Abstract: A system, method and computer-readable medium for balancing access among multiple logical partitions to the physical system resources of a computer system employing system virtualization. Each of the logical partitions is classified, initially during a startup period, in accordance with a level of allocated dispatch window utilization. Performance metrics of one or more of the physical system resources are determined in association with one or more of the logical partitions. The performance metrics determination is performed at a hardware level independent of programming interrupts. During a dispatch window in which a given set of the physical system resources are configured for allocation to one of the logical partitions, the given set of physical system resources are re-allocated to a replacement logical partition in accordance with the determined performance metrics associated with the replacement logical partition and the dispatch window utilization classification of the replacement logical partition.
    Type: Application
    Filed: March 28, 2007
    Publication date: October 2, 2008
    Inventors: Diane G. Flemming, Octavian F. Herescu, William A. Maron, Mysore S. Srinivas
  • Publication number: 20080244568
    Abstract: A method, system and computer program product enables the granular collection and utilization of hardware statistical samples for the efficient scheduling and allocation of data processing resources. In particular, a Partition Statistics Capture and Analysis (PSCA) utility utilizes special purpose registers to collect statistical samples, such as: (1) instructions completed; (2) Level2 (L2) cache misses; (3) cycles per instruction (CPI); and/or (4) other statistics selected based on the programming of the PSCA utility. Further, these statistical samples are utilized for the several purposes, including: (1) determining how long (time) the footprint of a partition takes to become established during the “cold start” period, i.e., during system instantiation; (2) detecting movement of the CPI curve in order to determine the (shifted) location of the onset of steady state (i.e., the knee) on the CPI curve; and (3) utilizing the statistical samples to guide dispatch decisions and make tuning recommendations.
    Type: Application
    Filed: March 28, 2007
    Publication date: October 2, 2008
    Inventors: DIANE G. FLEMMING, Octavian F. Herescu, William A. Maron, Mysore S. Srinivas
  • Publication number: 20080165800
    Abstract: A mechanism is provided in the operating system for recording context switch times. The operating system, the application, or the resource also includes a mechanism for recording response times. At the time of a request, the operating system may compare an average context switch time to an average response time corresponding to the request. The operating system may then decide whether to perform a context switch based on the comparison. Alternatively, the application may receive the average context switch time from the operating system and compare the average context switch time to an average response time corresponding to the request. The application may then decide whether to relinquish the processor or spin on the lock based on the comparison.
    Type: Application
    Filed: January 9, 2007
    Publication date: July 10, 2008
    Inventors: Wen-Tzer T. Chen, Men-Chow Chiang, William A. Maron, Mysore S. Srinivas
  • Patent number: 6845504
    Abstract: A system and method for efficiently managing lock contention for a central processing unit (CPU) of a computer system. The present invention uses both spinning and blocking (or undispatching) to manage threads when they are waiting to acquire a lock. In addition, the present invention intelligently determines when the program thread should spin and when the program thread should become undispatched. If it is determined that the program thread should become undispatched, the present invention provides efficient undispatching of program threads that improves throughput by reducing wait time to acquire the lock.
    Type: Grant
    Filed: February 8, 2001
    Date of Patent: January 18, 2005
    Assignee: International Business Machines Corporation
    Inventors: Hong L. Hua, Bret R. Olszewski, Mysore S. Srinivas, Nasr-Eddine Walehiane