Abstract: A method for testing a plurality of data bits includes the steps of accepting the plurality of data bits at the test circuit, and comparing first and second data bits from the plurality of data bits to determine if the first and second data bits have a common data value. A first comparison signal is generated responsive to the comparison of the first and second data bits. The first comparison signal has a first logic state when the first and second data bits have a common data value and a second logic state when the first and second data bits have different data values. Third and fourth data bits from the plurality of data bits are compared to determine if the third and fourth data bits have a common data value.

Abstract: A mode setting circuit and method of a semiconductor memory device for selectively enabling a specific operation mode out of preset operation modes. The mode setting circuit gates a signal set at an internal node of a row address buffer according to a mode setting control signal. The row address buffer receives a row address signal supplied from the exterior and generates a shaped row address. The latch circuit latches a signal generated from the gating circuit and generates a mode setting signal for enabling the specific operation mode in response to a variation in a specific signal of the internal node.