Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: Disclosed is an electronic device.

Abstract: A semiconductor chip includes a first semiconductor device and a second semiconductor device stacked and coupled through a unidirectional through electrode and a plurality of bidirectional through electrodes, wherein a through electrode in which a failure has occurred among the unidirectional through electrode and the plurality of bidirectional through electrodes is replaced based on a plurality of transfer control signals. The plurality of transfer control signals including failure information on the unidirectional through electrode and the plurality of bidirectional through electrodes.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: A semiconductor system including a semiconductor device configured to operate in various modes to generate output data having different patterns.

Abstract: A semiconductor chip includes a first semiconductor device and a second semiconductor device stacked over the first semiconductor device. The second semiconductor device is electrically connected to the first semiconductor device via a plurality of through electrodes. In a test mode, the first semiconductor device is configured to drive a first pattern of logic levels and a second pattern of logic levels through the plurality of through electrodes, configured to compare logic levels of a plurality of test data generated by the first and second patterns from the first and second semiconductor devices to generate a detection signal indicating that the plurality of through electrodes operated normally or abnormally.

Abstract: A semiconductor chip includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes an error detection circuit. The second semiconductor device is stacked with the first semiconductor device and is electrically connected to the first semiconductor device via a first through electrode and a second through electrode. The first and second semiconductor devices are configured to receive or output first data and second data via the second through electrode according to an operation mode and are configured to detect errors of the first data and the second data using the error detection circuit.

Abstract: A semiconductor device includes an error detection circuit configured to generate fixed data by fixing any one of a first group and a second group included in internal data to a preset level based on a burst chop signal and an internal command address in response to a read command, and generate an error detection signal by detecting an error of the fixed data; and a data output circuit configured to generate latch data by latching the internal data based on a first latch output control signal, and generate output data by serializing the latch data and the error detection signal based on a second latch output control signal.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs an error check enablement signal, an input clock signal, and input data to the second semiconductor device. The first semiconductor device receives an error check signal from the second semiconductor device. The second semiconductor device performs an error check operation for the input data based on the error check enablement signal and the input clock signal to generate the error check signal which is enabled when an error in the input data occurs.

Abstract: A semiconductor device includes a shift register and a control signal generation circuit. The shift register generates shifted pulses, wherein a number of the shifted pulses is controlled according to a mode of a burst length. The control signal generation circuit generates a control signal for setting a burst operation period according to a period during which the shifted pulses are created. The burst operation period is a period during which a burst operation is performed.

Abstract: An integrated circuit includes: a phase-shifted data signal generation circuit configured to generate a plurality of phase-shifted data signals from an input data signal based on at least one phase-shifted clock signal; a synchronization circuit configured to generate a plurality of synchronization data signals by applying the at least one phase-shifted clock signal to the plurality of phase-shifted data signals provided by the phase-shifted data signal generation circuit; and a control signal generation circuit configured to perform logic operations on the plurality of synchronization data signals to generate a phase control signal for controlling a phase of the at least one phase-shifted clock signal, and generate a frequency control signal for controlling a frequency of the at least one phase-shifted clock signal.

Abstract: A semiconductor device includes a shift register and a control signal generation circuit. The shift register generates shifted pulses, wherein a number of the shifted pulses is controlled according to a mode of a burst length. The control signal generation circuit generates a control signal for setting a burst operation period according to a period during which the shifted pulses are created. The burst operation period is a period during which a burst operation is performed.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: Disclosed is an electronic device.

Abstract: The present disclosure relates to a method for intuitively reproducing video contents through data structuring and the apparatus thereof, more specifically, which searches section by section the video contents edited and provided based on section with free search, hash tag, and/or bookmark, produces a new video contents from the searched sections of the video contents, and therefore promotes consumption of the video contents by providing reproduced video contents. The video contents can be edited and played by using a user interface intuitively figuring out the structure of video contents.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: A method of building a machine learning pipeline for predicting refractoriness of epilepsy patients is provided. The method includes providing electronic health records data; constructing a patient cohort from the electronic health records data by selecting patients based on failure of at least one anti-epilepsy drug; constructing a set features found in or derived from the electronic health records data; electronically processing the patient cohort to identify a subset of the features that are predictive for refractoriness for inclusion in a predictive model configured for classifying patients as refractory or non-refractory; and training the predictive computerized model to classify the patients having at least one anti-epilepsy drug failure based on likelihood of becoming refractory.

Abstract: A method of building a machine learning pipeline for predicting the efficacy of anti-epilepsy drug treatment regimens is provided.