Abstract: Disclosed are level shifters and methods of performing level shifting. In one embodiment, a level shifter is disclosed comprising an input, cross-coupled/latch circuitry, a first reference node, a second reference node, and output circuitry coupled between the cross-coupled/latch circuitry and an output, wherein the output circuitry sets the output signal to high based on rising edge of a second reference node and sets the output signal to low based on the rising edge of the first reference node. Further, in some implementations, the first reference node and the second reference node may have signals that are inverse to each other.

Abstract: Disclosed are level shifters and methods of performing level shifting. In one embodiment, a level shifter is disclosed comprising an input, cross-coupled/latch circuitry, a first reference node, a second reference node, and output circuitry coupled between the cross-coupled/latch circuitry and an output, wherein the output circuitry sets the output signal to high based on rising edge of a second reference node and sets the output signal to low based on the rising edge of the first reference node. Further, in some implementations, the first reference node and the second reference node may have signals that are inverse to each other.

Abstract: Disclosed are level shifters and methods of performing level shifting. In one embodiment, a level shifter is disclosed comprising an input, cross-coupled/latch circuitry, a first reference node, a second reference node, and output circuitry coupled between the cross-coupled/latch circuitry and an output, wherein the output circuitry sets the output signal to high based on rising edge of a second reference node and sets the output signal to low based on the rising edge of the first reference node. Further, the first reference node and the second reference node are symmetric nodes having signals that are inverse to each other.

Abstract: Disclosed are level shifters and methods of performing level shifting. In one embodiment, a level shifter is disclosed comprising an input, cross-coupled/latch circuitry, a first reference node, a second reference node, and output circuitry coupled between the cross-coupled/latch circuitry and an output, wherein the output circuitry sets the output signal to high based on rising edge of a second reference node and sets the output signal to low based on the rising edge of the first reference node. Further, the first reference node and the second reference node are symmetric nodes having signals that are inverse to each other.

Abstract: Embodiments include systems and methods for improving column selection functionality of memory circuits. Embodiments operate in context of memory bitcells having additional series pass gates (e.g., junction sharing transistors) coupled with a column select signal to form an integrated column select port. Such a column select port can provide each bitcell with column select functionality in a manner that has improved area and power performance over some conventional (added NOR or other logic) approaches. However, the added column select port can still tend to add area, add column select load, and degrade writability (e.g., due to certain charge-sharing effects). Some embodiments are described herein for addressing the area and column select load by sharing certain intermediate nodes among multiple, adjacent bitcells. Other embodiments can include additional ground-connected transistors in a manner that improves writability (e.g., and read noise margin) of the bitcell.

Abstract: Embodiments include systems and methods for improving column selection functionality of memory circuits. Embodiments operate in context of memory bitcells having additional series pass gates (e.g., junction sharing transistors) coupled with a column select signal to form an integrated column select port. Such a column select port can provide each bitcell with column select functionality in a manner that has improved area and power performance over some conventional (added NOR or other logic) approaches. However, the added column select port can still tend to add area, add column select load, and degrade writability (e.g., due to certain charge-sharing effects). Some embodiments are described herein for addressing the area and column select load by sharing certain intermediate nodes among multiple, adjacent bitcells. Other embodiments can include additional ground-connected transistors in a manner that improves writability (e.g., and read noise margin) of the bitcell.

Abstract: Apparatuses and methods for performing a data bus inversion operation (DBI) are described. An example apparatus includes a DBI circuit configured to, in parallel, determine preliminary DBI bits based on a block of data. Individual preliminary DBI bits are associated with respective sub-blocks of the block of data. The DBI circuit is further configured to serially determine DBI bits based on the preliminary DBI bits. Individual ones of the DBI bits are associated with respective ones of the sub-blocks. The DBI circuit is further configured to invert bits of individual sub-blocks responsive to the respective associated DBI bits having a particular logical value to provide DBI data. The apparatus further includes data outputs configured to serially output sub-blocks of the DBI data and the DBI bits.

Abstract: Systems, methods, and other embodiments associated with controlling when a sense amplifier is activated are described. In one embodiment, a device includes detection logic connected to a plurality of word lines in a memory and configured to generate a signal upon detecting one of the plurality of word lines being activated. The device includes a sense amplifier configured to read a value from a bit line associated with an activated word line of the plurality of word lines upon receiving the signal.

Abstract: Apparatuses and methods for performing a data bus inversion operation (DBI) are described. An example apparatus includes a DBI circuit configured to, in parallel, determine preliminary DBI bits based on a block of data. Individual preliminary DBI bits are associated with respective sub-blocks of the block of data. The DBI circuit is further configured to serially determine DBI bits based on the preliminary DBI bits. Individual ones of the DBI bits are associated with respective ones of the sub-blocks. The DBI circuit is further configured to invert bits of individual sub-blocks responsive to the respective associated DBI bits having a particular logical value to provide DBI data. The apparatus further includes data outputs configured to serially output sub-blocks of the DBI data and the DBI bits.

Abstract: Systems, methods, and other embodiments associated with controlling when a sense amplifier is activated are described. In one embodiment, a device includes detection logic connected to a plurality of word lines in a memory and configured to generate a signal upon detecting one of the plurality of word lines being activated. The device includes a sense amplifier configured to read a value from a bit line associated with an activated word line of the plurality of word lines upon receiving the signal.

Abstract: A refresh control circuit and method generates a refresh signal in response to one of a plurality of clock signals and a temperature signal. The clock signals and temperature signal may be synchronized to prevent an incomplete refresh operation at a trip point of a temperature sensor. In one embodiment, a pulse generator may generate a temperature sensor enable signal in response to the clock signals when the clock signals are synchronized. In other embodiments, the temperature signal may be latched to prevent a transition in the refresh signal during a refresh operation. The temperature signal may be latched in response to one of the clock signals or the refresh signal.

Abstract: A semiconductor integrated circuit device has a fuse device that can be electrically disconnected without a breakage caused by using a laser beam or current. The semiconductor integrated circuit device employs, as the fuse device for storing status information, a MOSFET of a single polysilicon EEPROM-type cell manufactured through a process of fabricating a volatile semiconductor memory cell array.

Abstract: A reset signal generator includes an output unit, a trip signal generator, an inverter unit, and a variation reducing unit. The output unit generates a reset signal from a pre-reset signal, and the reset signal follows a supply voltage signal before transitioning to a ground level when the supply voltage signal reaches a tripping voltage. The variation reducing unit is coupled to the inverter unit for reducing a range of the tripping voltage with temperature variations.

Abstract: A memory device includes a bit line sense amplifier, a command decoder configured to generate an internal control signal indicating an operating mode of the memory device, and a bit line sense amplifier controller configured to selectively apply an external voltage as a supply voltage to the bit line sense amplifier in response to the internal control signal.

Abstract: Internal voltage generators are provided, as well as methods of overdriving an internal voltage generation circuit. Embodiments of the internal voltage generator comprise a first driver for receiving an external voltage to supply an internal voltage to the internal circuit in response to an input voltage; a comparator for comparing a reference voltage with a fed-back internal voltage to generate the input voltage of the first driver; a variable pulse generating circuit responsive to an input pulse; and a second driver for dropping the input voltage of the first driver to a ground voltage in response to the variable pulse produced by the variable pulse generating circuit. The internal voltage generator can generate the internal voltage of a relatively constant level without regard to increase of the external voltage or frequency of an operating signal.

Abstract: A reset signal generator includes an output unit, a trip signal generator, an inverter unit, and a variation reducing unit. The output unit generates a reset signal from a pre-reset signal, and the reset signal follows a supply voltage signal before transitioning to a ground level when the supply voltage signal reaches a tripping voltage. The variation reducing unit is coupled to the inverter unit for reducing a range of the tripping voltage with temperature variations.

Abstract: A refresh control circuit and method generates a refresh signal in response to one of a plurality of clock signals and a temperature signal. The clock signals and temperature signal may be synchronized to prevent an incomplete refresh operation at a trip point of a temperature sensor. In one embodiment, a pulse generator may generate a temperature sensor enable signal in response to the clock signals when the clock signals are synchronized. In other embodiments, the temperature signal may be latched to prevent a transition in the refresh signal during a refresh operation. The temperature signal may be latched in response to one of the clock signals or the refresh signal.

Abstract: A memory device includes a bit line sense amplifier, a command decoder configured to generate an internal control signal indicating an operating mode of the memory device, and a bit line sense amplifier controller configured to selectively apply an external voltage as a supply voltage to the bit line sense amplifier in response to the internal control signal.

Abstract: A semiconductor integrated circuit device has a fuse device that can be electrically disconnected without a breakage caused by using a laser beam or current. The semiconductor integrated circuit device employs, as the fuse device for storing status information, a MOSFET of a single polysilicon EEPROM-type cell manufactured through a process of fabricating a volatile semiconductor memory cell array.

Abstract: A temperature sensing circuit has numerous trip points in conformity with a temperature change without adding decrease resistance branches, so as to obtain a fine control based on the temperature change. Accordingly, when employed in a semiconductor memory device, the temperature sensing circuit substantially reduces the consumption of refresh electrical power in a stand-by state without decreasing the reliability of the semiconductor memory device.