Abstract: A system includes memory banks that store data and a data path coupled to the memory banks that transfers the data. The system also includes a latch that gates the data path based on a clock signal in the system. The system further includes interface circuitry coupled to the data path that sends an instruction to the memory banks to transmit the data on the data path in response to receiving a first rising edge of the clock signal. The interface circuitry also outputs gated data in response to receiving a second rising edge of the clock signal. The latch gates the data path to store the gated data in response to receiving a falling edge of the clock signal.

Abstract: Devices and methods include receiving a command at a command interface to assert on-die termination (ODT) during an operation. An indication of a shift mode register value is received via an input. The shift mode register value corresponds to a number of shifts of a rising edge of the command in a backward direction. A delay pipeline delays the received command the number of shifts in the backward direction to generate a shifted rising edge command signal. Combination circuitry is configured to combine a falling edge command signal with the shifted rising edge command signal to form a transformed command.

Abstract: A system that incorporates teachings of the subject disclosure may include, for example, a method for depositing a first material that substantially covers a nanoheater, applying a signal to the nanoheater to remove a first portion of the first material covering the nanoheater to form a trench aligned with the nanoheater, depositing a second material in the trench, and removing a second portion of the first material and a portion of the second material to form a nanowire comprising a remaining portion of the second material covering the nanoheater along the trench. Additional embodiments are disclosed.

Abstract: A system that incorporates teachings of the subject disclosure may include, for example, a method for depositing a first material that substantially covers a nanoheater, applying a signal to the nanoheater to remove a first portion of the first material covering the nanoheater to form a trench aligned with the nanoheater, depositing a second material in the trench, and removing a second portion of the first material and a portion of the second material to form a nanowire comprising a remaining portion of the second material covering the nanoheater along the trench. Additional embodiments are disclosed.

Abstract: The present invention provides a novel phenylpropionic acid derivative and a PPAR-? modulator comprising the same as an active ingredient. The phenylpropionic acid derivative of the present invention has modulatory action on function of PPAR-? and then exhibits hypoglycemic, hypolipidemic and insulin resistance-reducing effects on PPAR-mediated diseases or disorders. Therefore, the present invention is prophylactically or therapeutically effective for diabetes and metabolic diseases.

Abstract: A redundancy system for disabling access to normal memory elements when memory addresses corresponding to those normal memory elements match programmed redundancy addresses before the memory addresses and the programmed redundancy addresses are compared. Access to the normal memory elements is disabled based on the programmed redundancy addresses.

Abstract: A DC superconducting interference device (SQUID) utilizes intrinsic Josephson tunnel junctions formed naturally in stacks of high-Tc superconducting single crystals, where the double-side cleaving technique is used to define a ring-shaped high-Tc superconducting structure with two stacks of intrinsic Josephson junctions inserted in the ring.

Abstract: A DC superconducting interference device (SQUID) utilizes intrinsic Josephson tunnel junctions formed naturally in stacks of high-Tc superconducting single crystals, where the double-side cleaving technique is used to define a ring-shaped high-Tc superconducting structure with two stacks of intrinsic Josephson junctions inserted in the ring.

Abstract: Provided is a THz electromagnetic wave radiation and detection device using a high-Tc superconductor. The device includes an electromagnetic generation unit which is formed of a superconducting single crystal mesa structure where intrinsic Josephson junctions of superconducting layers and insulating layers are serially stacked and which can excite a THz electromagnetic wave; an insulating unit which contacts the electromagnetic wave generation unit and is not conductive; and an electromagnetic wave detection unit which contacts the insulating unit, is formed of the superconducting single crystal mesa structure where intrinsic Josephson junctions of the superconducting layers and the insulating layers are serially stacked and which can detect the THz electromagnetic wave. The radiation of the THz electromagnetic wave excited in the electromagnetic wave generation unit is coupled to the electromagnetic wave detection unit through the insulating unit instead of being emitted into the free space (air).

Abstract: A process for manufacturing nickel chloride is disclosed which is used as the raw material for manufacturing Zn--Ni coated steel plates, for electroless Ni plating industries, for electronic components, and for a high purity chemical additive Ni powder. That is, the invention discloses a process for manufacturing high purity nickel chloride (NiCl.sub.2) by utilizing a waste nickel anode which is obtained from an electroplating factory of a steel manufacturing plant. The process for manufacturing high purity nickel chloride includes the steps of: pre-treating a waste nickel anode to remove impurities adhered on the surface thereof; working the pre-treated waste nickel anode so as to provide an increased specific surface area; putting the worked waste nickel anode into an aqueous hydrochloric acid solution of 10-35% so as for the equivalence ratios of Ni, HCl and NiCl.sub.2 to be 1.0 or more, and dissolving the worked waste nickel anode at a reaction temperature of 20.degree.-80 C.

Abstract: A semiconductor integrated device is disclosed which is capable of selectively executing a memory test and a logic test. The device includes a logic part for realizing a plurality of operation functions in logic, a memory part having a given integration and for storing data, a pad part including a pad for inputting/outputting a control signal according to respective tests, a switch part respectively connected to the logic part, the memory part, and the pad part, and a switch control part for controlling the switch part to thereby selectively control the memory test and the logic test. The semiconductor integrated device according to the present invention is capable of performing a separate logic test by dividing a memory fault and a logic fault on a memory testing path. The semiconductor integrated device has a memory signal path, a logic signal path, and a pad path which are selectively used.

Abstract: A power supply arrangement for a semiconductor chip includes, in a first preferred embodiment, a power supply voltage line, a ground voltage line, an intermediate voltage line, a plurality of first noise reduction capacitors connected between the intermediate voltage line and the power supply voltage line, and a plurality of second noise reduction capacitors connected between the intermediate voltage line and the ground voltage line. In a second preferred embodiment, the power supply arrangement includes a power supply voltage line, a ground voltage line, a quiet power supply voltage line, a quiet ground voltage line, a plurality of first noise reduction capacitors connected between the power supply voltage line and the quiet ground voltage line, and a plurality of second noise reduction capacitors connected between the ground voltage line and the quiet power supply voltage line.

Abstract: A data sensing circuit for a semiconductor memory device having complementary bit lines, including a PMOS sense amplifier connected between the complementary bit lines, an NMOS sense amplifier connected between the complementary bit lines, a bit line equalization and precharge circuit connected between the complementary bit lines, a sense amplifier equalization and precharge circuit connected between sensing control nodes of the PMOS and NMOS sense amplifiers, a plurality of first capacitors, a plurality of second capacitors, a plurality of first fuses connected between the sensing control node of the PMOS sense amplifier and respective ones of the first capacitors, a plurality of second fuses connected between the sensing control node of the NMOS sense amplifier and respective ones of the second capacitors.

Abstract: A circuit which is particularly useful as a chip initialization signal generating circuit for initializing the circuits of a semiconductor memory device includes a time delay circuit for generating a second signal a predetermined time after a first signal, e.g., a power supply voltage, is applied thereto, a first inverter for generating a third signal having a first logic level when the second signal is below a trip point level of the first inverter, and a second logic level when the second signal is above the trip point level, and, a trip point level raising circuit coupled to the first inverter for raising the trip point level.

Abstract: There is provided a spare column selection circuit comprising a line switching pair arranged between a spare input/output line pair connected to a spare bit line and a normal input/output line pair connected to a normal bit line pair. The line switching pair are driven by an output of a spare column decoder. A normal line pull-up pair are connected to the corresponding normal input/output line so as to be driven by the output of the spare column decoder. An inverter produces a clock signal having an inverted signal phase against a clock from a spare column decoder, and the inverted clock signal connects the spare input/output line pair to the spare bit line pair.