Abstract: Provided is a bioresorbable stent including a stent substrate including a bioresorbable polymer and a contrast medium containing an iodine component, coated on the stent substrate. Since the stent according to the present invention is absorbed in and removed from the human body after a predetermined time, it has excellent biodegradability since it has improved radiopacity by iodine contrast medium coating, it has a high radiography contrast and is very efficient even when a procedure is performed with real time radiography, and since it has low foreshortening and high flexibility, radial force, and re-coil, it may be useful for insertion into a blood vessel having a small diameter, an acute occlusive lesion, an imminent occlusive lesion, and the like.

Abstract: Provided are a silicon nitride film etching composition, a method of etching a silicon nitride film using the same, and a manufacturing method of a semiconductor device. Specifically, a silicon nitride film may be stably etched with a high selection ratio relative to a silicon oxide film, and when the composition is applied to an etching process at a high temperature and a semiconductor manufacturing process, not only no precipitate occurs but also anomalous growth in which the thickness of the silicon oxide film is rather increased does not occur, thereby minimizing defects and reliability reduction.

Abstract: A capacitor component includes a body including dielectric layers, first and second internal electrodes, laminated in a first direction, facing each other, and first and second cover portions, disposed on outermost portions of the first and second internal electrodes, and first and second external electrodes, respectively disposed on both external surfaces of the body in a second direction, perpendicular to the first direction, and respectively connected to the first and second internal electrodes. An indentation including a glass is disposed at at least one of boundaries between the first internal electrodes and the first external electrode or one of boundaries between the second internal electrodes and the second external electrode.

Abstract: A vehicle seat reinforcement device includes a leg portion mounted on a floor panel, a seat cushion frame slidably mounted on the leg portion, and a load reinforcing structure connected between the leg portion and the seat cushion frame, wherein when a seat belt anchorage load is transferred to the seat cushion frame, the seat cushion frame is locked to the leg portion by the load reinforcing structure.

Abstract: An image encoding/decoding method is provided. An image decoding method of the present invention may comprise deriving an intra-prediction mode of a current luma block, deriving an intra-prediction mode of a current chroma block based on the intra-prediction mode of the current luma block, generating a prediction block of the current chroma block based on the intra-prediction mode of the current chroma block, and the deriving of an intra-prediction mode of a current chroma block may comprise determining whether or not CCLM (Cross-Component Linear Mode) can be performed for the current chroma block.

Abstract: A background music providing method includes: based on a user command for executing a content recognition mode being received, obtaining a data corresponding to the content, reproduced on the display apparatus, in the content recognition mode; transmitting the obtained data to an external source; obtaining information corresponding to the content based on the data from the external source; and displaying a result UI corresponding to the obtained information on the display apparatus.

Abstract: A secondary battery comprises an electrode assembly, a can, and an insulator. The electrode assembly includes a first electrode, a separator, and a second electrode alternately stacked and wound. The can has an accommodation part accommodating the electrode assembly therein, and the can comprises a first can and a second can having cylindrical shapes open in a direction facing each other. The insulator insulates an overlapping portion between the first can and the second can. The first can is electrically connected to the first electrode, and the second can is electrically connected to the second electrode. The insulator has a short-circuit induction through-part defined by a through-hole or a cutoff line, such that a short circuit occurs between the first can and the second can through the short-circuit induction through-part when it is deformed in shape as heat or a pressure is applied to contract or expand the insulator.

Abstract: The present invention relates to a fire resistant paint composition, to a production method for same and to a painting method for a fire resistant paint using same, and, one example of implementation of the present invention can provide a fire resistant paint composition comprising: between 70 and 95 wt. % of a binder; between 1 and 10 wt. % of an aerogel; between 1 and 5 wt. % of a foaming agent; and the remainder of water, and can provide a production method for same and a painting method for a fire resistant paint using same.

Abstract: A wafer-level chip-scale package includes: a power semiconductor comprising a first semiconductor device formed on a semiconductor substrate, and a second semiconductor device formed on the semiconductor substrate; a common drain electrode connected to the first semiconductor device and the second semiconductor device; a first source metal bump formed on a surface of the first semiconductor device; and a second source metal bump formed on the surface of the second semiconductor device; wherein the first source metal bump, the common drain electrode, and the second source metal bump form a current path in an order of the first source metal bump, the common drain electrode, and the second source metal bump.

Abstract: A wafer-level chip-scale package includes: a power semiconductor comprising a first semiconductor device formed on a semiconductor substrate, and a second semiconductor device formed on the semiconductor substrate; a common drain electrode connected to the first semiconductor device and the second semiconductor device; a first source metal bump formed on a surface of the first semiconductor device; and a second source metal bump formed on the surface of the second semiconductor device; wherein the first source metal bump, the common drain electrode, and the second source metal bump form a current path in an order of the first source metal bump, the common drain electrode, and the second source metal bump.

Abstract: The description relates to a semiconductor die having a stacking structure of silicon-metallic conductive layer-silicon, and the semiconductor die according to embodiments includes a stacking structure of first semiconductor layer-metallic conductive layer-second semiconductor layer, and first and second power semiconductor devices in the first semiconductor layer, in which the first power semiconductor device includes a first source bump and a first gate bump, first trench gate electrodes under the first source bump, and a first channel among the plurality of first trench gate electrodes, in which the second power semiconductor device includes a second source bump and a second gate bump, second trench gate electrodes under the second source bump, and a second channel among the plurality of second trench gate electrodes, and in which the metallic conductive layer includes a metal layer.

Abstract: A wafer-level chip-scale package includes: a power semiconductor comprising a first semiconductor device formed on a semiconductor substrate, and a second semiconductor device formed on the semiconductor substrate; a common drain electrode connected to the first semiconductor device and the second semiconductor device; a first source metal bump formed on a surface of the first semiconductor device; and a second source metal bump formed on the surface of the second semiconductor device; wherein the first source metal bump, the common drain electrode, and the second source metal bump form a current path in an order of the first source metal bump, the common drain electrode, and the second source metal bump.

Abstract: A multi-chip package of power semiconductor includes a lead frame, a first segment group, a second segment group, a first power semiconductor chip and a second power semiconductor chip. The lead frame includes a first segment group having a first gate segment, a first source segment, and a first drain segment that are separated from each other. The second segment group has a second gate segment, a second source segment, and a second drain segment that are separated from each other. The first power semiconductor chip is formed on the first segment group. The second power semiconductor chip is formed on the second segment group. The first source segment is physically connected to the second drain segment.

Abstract: The description relates to a semiconductor die having a stacking structure of silicon-metallic conductive layer-silicon, and the semiconductor die according to embodiments includes a stacking structure of first semiconductor layer-metallic conductive layer-second semiconductor layer, and first and second power semiconductor devices in the first semiconductor layer, in which the first power semiconductor device includes a first source bump and a first gate bump, first trench gate electrodes under the first source bump, and a first channel among the plurality of first trench gate electrodes, in which the second power semiconductor device includes a second source bump and a second gate bump, second trench gate electrodes under the second source bump, and a second channel among the plurality of second trench gate electrodes, and in which the metallic conductive layer includes a metal layer.

Abstract: The description relates to a semiconductor die having a stacking structure of silicon-metallic conductive layer-silicon, and the semiconductor die according to embodiments includes a stacking structure of first semiconductor layer-metallic conductive layer-second semiconductor layer, and first and second power semiconductor devices in the first semiconductor layer, in which the first power semiconductor device includes a first source bump and a first gate bump, first trench gate electrodes under the first source bump, and a first channel among the plurality of first trench gate electrodes, in which the second power semiconductor device includes a second source bump and a second gate bump, second trench gate electrodes under the second source bump, and a second channel among the plurality of second trench gate electrodes, and in which the metallic conductive layer includes a metal layer.

Abstract: The description relates to a semiconductor die having a stacking structure of silicon-metallic conductive layer-silicon, and the semiconductor die according to embodiments includes a stacking structure of first semiconductor layer-metallic conductive layer-second semiconductor layer, and first and second power semiconductor devices in the first semiconductor layer, in which the first power semiconductor device includes a first source bump and a first gate bump, first trench gate electrodes under the first source bump, and a first channel among the plurality of first trench gate electrodes, in which the second power semiconductor device includes a second source bump and a second gate bump, second trench gate electrodes under the second source bump, and a second channel among the plurality of second trench gate electrodes, and in which the metallic conductive layer includes a metal layer.

Abstract: A multi-chip package of power semiconductor includes a lead frame, a first segment group, a second segment group, a first power semiconductor chip and a second power semiconductor chip. The lead frame includes a first segment group having a first gate segment, a first source segment, and a first drain segment that are separated from each other. The second segment group has a second gate segment, a second source segment, and a second drain segment that are separated from each other. The first power semiconductor chip is formed on the first segment group. The second power semiconductor chip is formed on the second segment group. The first source segment is physically connected to the second drain segment.

Abstract: A wafer-level chip-scale package includes: a power semiconductor comprising a first semiconductor device formed on a semiconductor substrate, and a second semiconductor device formed on the semiconductor substrate; a common drain electrode connected to the first semiconductor device and the second semiconductor device; a first source metal bump formed on a surface of the first semiconductor device; and a second source metal bump formed on the surface of the second semiconductor device; wherein the first source metal bump, the common drain electrode, and the second source metal bump form a current path in an order of the first source metal bump, the common drain electrode, and the second source metal bump.

Abstract: Thermally radiating heat sinks are soldered directly beneath individual LEDs and other heat generating electronic components on the opposite side of an FR4 circuit board and thermally coupled to the heat source through multiple micro-vias. The micro-vias are filled with solder in order to increase the thermal transmission of heat energy through the circuit board to the heat sinks The circuit board thickness is minimized to further reduce the thermal resistance of the transmission path. The method employed facilitates the heat transfer away from high-powered LEDs and other heat generating circuitry without spreading the heat energy to thermally sensitive electronic circuits and without the need for expensive substrates commonly employed to dissipate heat in electronic circuits. The method is adapted for LED lighting circuits and preferably to industry standard bulb sizes such as MR11, MR16, R20, PAR30, PAR38, and PAR56.

Abstract: A method of fabricating a flexible film is provided. The method includes opening an imide ring on a polyimide film; applying a catalyst to the polyimide film; removing tin from the catalyst; forming a first metal film on the polyimide film; drying the polyimide film having the first metal film at a temperature of 110-200° C.; and forming a second metal film on the first metal film. According to the method, it is possible to fabricate a flexible film without a requirement of an adhesive layer and thus provide a flexible film with excellent physical properties such as excellent plating properties, high adhesive strength, high heat resistance, high drug resistance, excellent migration properties and high folding endurance.