Abstract: An aircraft assembly system includes a jig; and a position adjuster connected to the jig and configured to adjust a position of the jig, wherein the jig includes a ball stud between the jig and the position adjuster, and the position adjuster includes a socket in which at least a portion of the ball stud is accommodated and in which the ball stud is rotatably fastened.

Abstract: Example embodiments include a battery insulation sheet having a structure in which a first substrate, an aerogel layer, and a second substrate are laminated, wherein opposite surfaces of the aerogel layer is in contact with the first substrate or the second substrate adjacent thereto. Example embodiments also include a method of manufacturing a battery insulation sheet, and a battery module including the battery insulation sheet.

Abstract: A method of securing input data using random number data for a security keypad according to the present invention includes (a) a step of generating randomly server random number data by a main server, (b) a step of generating, by a client, client random number data corresponding to each input character input through a security keypad from a random number table generated by using the server random number data, and (c) a step of generating, by the main server, final random number data and a final random number table by using the client random number data, and extracting and generating plain text data from the final random number table.

Abstract: Disclosed is an ozone water supplying unit capable of maintaining a stable ozone concentration of ozone water supplied to a substrate, and a substrate treating apparatus including the same. The substrate treating apparatus includes: a chamber for liquid-treating a substrate loaded into a treating space with a liquid containing ozone water; and an ozone water supplying unit for supplying ozone water to the treating space, in which the ozone water supplying unit includes: an ozone water generator for generating ozone water; an ozone water supply line for supplying ozone water generated by the ozone water generator to the treating space; and a cooler provided in the ozone water supply line to cool the ozone water flowing through the ozone water supply line.

Abstract: A non-volatile memory chip comprises a cell region that includes a first surface, a second surface opposite to the first surface, a first cell structure, and a second cell structure spaced apart from the first cell structure; a peripheral circuit region on the first surface of the cell region, and that includes a first peripheral circuit connected to the first cell structure, a second peripheral circuit connected to the second cell structure, and a connection circuit between the first and second peripheral circuits; a through via between the first and second cell structures and that extends from the second surface of the cell region to the connection circuit of the peripheral circuit region; a redistribution layer that covers the through via on the second surface of the cell region, is connected to the through via, and extends along the second surface; and a chip pad connected to the redistribution layer.

Abstract: In an assembly system of an aircraft including a fuselage and a wing, the aircraft assembly system may include: a jig unit coupled to the wing to move integrally with the wing; a transfer unit connected to the jig unit and transferring the wing toward the fuselage; a position adjusting unit detachably connected to the jig unit and adjusting a position of the jig unit; and a measuring unit configured for measuring positions of the fuselage and the wing, wherein the fuselage may be relatively fixed to the movement of the wing, wherein the measuring unit may be configured to set a fuselage coordinate system and a wing coordinate system for the fuselage and the wing, respectively, wherein the position adjusting unit may be configured to move the jig unit so that the wing coordinate system coincides with the fuselage coordinate system.

Abstract: A nonvolatile memory device includes a memory cell region including first metal pads, and a peripheral circuit region. The peripheral circuit region includes second metal pads, a signal storage circuit that stores control signals and a data signal received from external of the nonvolatile memory device, a debugging information generator that generates debugging information based on the stored control signals and the stored data signal, and a debugging information register that outputs the debugging information in response to a debugging information external of the nonvolatile memory device. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads.

Abstract: Proposed is a cover structure with a double cover structure and a shooting case of munition having the same. The cover structure with a double cover structure includes: a shooting case main body having an inner space with an open upper side; a cover member seated on the open upper side of the shooting case main body to seal the open upper side; and a cover fixing member coupled to the shooting case main body to fix a position of the cover member, so that the position of the cover member is strongly fixed while simplifying a structure by the double cover structure to increase an internal pressure of the shooting case, thereby increasing a range of munition and maintaining performance of munition.

Abstract: A nonvolatile memory device includes a memory cell region including first metal pads, and a peripheral circuit region. The peripheral circuit region includes second metal pads, a signal storage circuit that stores control signals and a data signal received from external of the nonvolatile memory device, a debugging information generator that generates debugging information based on the stored control signals and the stored data signal, and a debugging information register that outputs the debugging information in response to a debugging information external of the nonvolatile memory device. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads.

Abstract: An operation method of a nonvolatile memory device includes receiving control signals and a data signal from external of the nonvolatile memory device, generating debugging information based on the control signals and the data signal, receiving a debugging information request from external of the nonvolatile memory device, and outputting the debugging information in response to the debugging information request.

Abstract: A read method of a nonvolatile memory device includes reading data from a selected memory area of the nonvolatile memory device according to a first read voltage; detecting and correcting an error of the read data; and deciding a second read voltage for reading the selected memory area when an error of the read data is uncorrectable. The second read voltage is decided according to either the number of logical 0s or 1s included in the read data, or a ratio of logical 1s to logical 0s in the read data.

Abstract: An operation method of a nonvolatile memory device includes receiving control signals and a data signal from external of the nonvolatile memory device, generating debugging information based on the control signals and the data signal, receiving a debugging information request from external of the nonvolatile memory device, and outputting the debugging information in response to the debugging information request.

Abstract: Provided is a smart raw cotton total management system and more particularly, a smart raw cotton total management system which promotes efficiency of raw cotton management by providing a variety of evaluation information on the raw cotton purchased by the member to the member side and totally manages a raw cotton member and a raw cotton supplier by providing purchase prior information to the member when requesting the raw cotton purchase of the member to perform reasonable raw cotton purchase and transaction.

Abstract: A nonvolatile memory device includes a memory cell array having memory cells, a row decoder circuit connected to the memory cells through word lines, a page buffer circuit connected to the memory cells through bit lines, and a control circuit controlling the row decoder circuit and the page buffer circuit to repeatedly perform an erase loop including an erase and an erase verification with respect to the memory cells. The control circuit is configured to select one of an increase and a decrease of an erase voltage according to a result of the erase verification of a current erase loop and apply the controlled erase voltage to the memory cells in the erase operation of a subsequent erase loop.

Abstract: A nonvolatile memory device includes a memory cell array having memory cells, a row decoder circuit connected to the memory cells through word lines, a page buffer circuit connected to the memory cells through bit lines, and a control circuit controlling the row decoder circuit and the page buffer circuit to repeatedly perform an erase loop including an erase and an erase verification with respect to the memory cells. The control circuit is configured to select one of an increase and a decrease of an erase voltage according to a result of the erase verification of a current erase loop and apply the controlled erase voltage to the memory cells in the erase operation of a subsequent erase loop.

Abstract: A nonvolatile memory device includes a memory cell array having memory cells, a row decoder circuit connected to the memory cells through word lines, a page buffer circuit connected to the memory cells through bit lines, and a control circuit controlling the row decoder circuit and the page buffer circuit to repeatedly perform an erase loop including an erase and an erase verification with respect to the memory cells. The control circuit is configured to select one of an increase and a decrease of an erase voltage according to a result of the erase verification of a current erase loop and apply the controlled erase voltage to the memory cells in the erase operation of a subsequent erase loop.

Abstract: A memory device includes a memory cell array having a plurality of memory cells, and a page buffer unit including a plurality of page buffers configured to store a plurality of pieces of data sequentially read from some of the plurality of memory cells at different read voltage levels, respectively, and to perform a logic operation on the plurality of pieces of data, respectively. The memory device further includes a counting unit configured to count the number of memory cells that exist in each of a plurality of sections defined by the different read voltage levels, based on results of the logic operation.

Abstract: Provided is a method of operating a non-volatile memory device including a plurality of strings, each string including a plurality of memory cells vertically stacked on a substrate. The method includes performing an erase operation on memory cells corresponding to a plurality of string selection lines, performing an erase verification operation on first strings connected to a first string selection line from among the plurality of string selection lines, storing fail column information corresponding to a first fail string, which is erase-failed, from among the first strings, and performing an erase verification operation on second strings connected to a second string selection line from among the plurality of string selection lines, when the first strings are erase-passed.

Abstract: A nonvolatile memory device includes a memory cell array having memory cells, a row decoder circuit connected to the memory cells through word lines, a page buffer circuit connected to the memory cells through bit lines, and a control circuit controlling the row decoder circuit and the page buffer circuit to repeatedly perform an erase loop including an erase and an erase verification with respect to the memory cells. The control circuit is configured to select one of an increase and a decrease of an erase voltage according to a result of the erase verification of a current erase loop and apply the controlled erase voltage to the memory cells in the erase operation of a subsequent erase loop.

Abstract: A non-volatile memory device receives a start command through a command line, receives an address through an address line, receives at least one setting value through the address line, receives a confirm command corresponding to the start command through the command line, sets at least one parameter of the non-volatile memory device as the setting value based on the start command, a number of the setting value, and the confirm command, and executes an operation that corresponds to the start command, on a memory cell that corresponds to the address, based on the set parameter.