Abstract: The present disclosure a method of decoding a polar code based on a shared node, the method includes extracting an input node from target data that are data to be decoded, by an extractor, sorting the input node as one of a first node of which the pattern of the frozen bit satisfies a predetermined first reference, a second node of which the pattern of the information bit satisfies a predetermined second reference, and a third node that is not the first node and the second node, by a sorter, calculating at least one codeword candidate and at least one path metric that correspond to the input node in accordance with the sorting result by a calculator, finishing decoding the target data by iterating the extracting, the sorting as one, and the calculating of at least one path metric by a controller.

Abstract: The present disclosure a method of decoding a polar code based on a shared node, the method includes extracting an input node from target data that are data to be decoded, by an extractor, sorting the input node as one of a first node of which the pattern of the frozen bit satisfies a predetermined first reference, a second node of which the pattern of the information bit satisfies a predetermined second reference, and a third node that is not the first node and the second node, by a sorter, calculating at least one codeword candidate and at least one path metric that correspond to the input node in accordance with the sorting result by a calculator, finishing decoding the target data by iterating the extracting, the sorting as one, and the calculating of at least one path metric by a controller.

Abstract: Disclosed is a high efficiency video coding (HEVC) encoding device including a candidate group updater configured to select a plurality of representative modes as a candidate group from among intra-prediction modes and update the candidate group using a plurality of minimum modes selected from the candidate group, the plurality of representative modes each representing a range where there is an optimal mode, and an optimal mode selector configured to select any one mode as an optimal mode from among a plurality of minimum modes selected from the updated candidate group.

Abstract: According to another exemplary embodiment of the present disclosure, a method for monitoring a pressure in a biliary tract includes: receiving a measured value of a pressure in a biliary tract from a stent for a biliary tract having a pressure sensor mounted therein, by a subcutaneous implant medical device; collecting the measured value of the pressure at a predetermined cycle and transmitting collected information to an external device, by the subcutaneous implant medical device; and analyzing the collected information to expect a timing of biliary obstruction, and providing expected information to the patient, by the external device.

Abstract: Disclosed are an apparatus and a method for a convolution operation of a convolution neural network. An apparatus for a convolution operation of a convolution neural network according to an exemplary embodiment of the present disclosure includes: an operation control unit that determines whether or not to perform the convolution operation based on the number of ‘0’ in a partial region of an input feature map; and an operation unit that performs the convolution operation of the partial region according to the determination of the operation control unit.

Abstract: Disclosed are a method and an apparatus for jaundice diagnosis based on an image. The method for jaundice diagnosis based on an image includes: receiving a jaundice diagnostic image acquired by photographing both a specific body part of a user and a reference object at a place where the user is positioned at present; generating color distortion information indicating a color distortion degree of the reference object included in the jaundice diagnostic image; generating a jaundice diagnostic correction image by correcting color distortion of the jaundice diagnostic image based on the color distortion information; and diagnosing a jaundice symptom for the user by using the jaundice diagnostic correction image.

Abstract: Disclosed are image based jaundice analyzing method and apparatus. The image based jaundice analyzing method according to an exemplary embodiment of the present disclosure includes: receiving an image for jaundice diagnosis obtained by photographing a specific body part of a user and a reference object in a location where the user is currently located; generating color distortion information representing a degree of color distortion of the reference object included in the image for jaundice diagnosis; generating a correction image for jaundice diagnosis by correcting the color distortion of the image for jaundice diagnosis based on the color distortion information; and diagnosing a jaundice symptom of the user using the correction image for jaundice diagnosis.

Abstract: Provided is a history based CU depth determining method. A history based CU depth determining method according to an exemplary embodiment of the present disclosure is a method for determining depths of a plurality of coding units (CU) included in each of a plurality of coding tree units (CTU) which configures a frame of a video, including: dividing a plurality of previous CTUs of a plurality of previous frames which are the same position as a current CTU of a current frame into a plurality of areas to generate depth history information including information of a CU depth for each of the plurality of areas; determining a plurality of depth candidates for a CU depth for each of the plurality of areas of the current CTU, based on the depth history information; and selecting an optimal CU depth among the plurality of depth candidates for each of the plurality of areas of the current CTU, through a rate-distortion cost (RD-cost) calculation.

Abstract: Provided is a method of decoding a low-density parity-check code (LDPC). The decoding method including an initialization process, a check node update process, a variable node update process, a tentative decoding process, and a parity check process, for a plurality of check nodes and a plurality of variable nodes, further includes detecting at least one inactive variable nodes that do not require variable node update among the variable nodes, the variable node update process is performed only on active variable nodes except for the inactive variable node, and the check node update process is performed without using the inactive variable node.

Abstract: Disclosed is a high efficiency video coding (HEVC) encoding device including a candidate group updater configured to select a plurality of representative modes as a candidate group from among intra-prediction modes and update the candidate group using a plurality of minimum modes selected from the candidate group, the plurality of representative modes each representing a range where there is an optimal mode, and an optimal mode selector configured to select any one mode as an optimal mode from among a plurality of minimum modes selected from the updated candidate group.

Abstract: Provided are a motion estimation method and a motion estimation apparatus. The motion estimation apparatus includes a first register storing information on whether to detect first detection positions, a second register storing information on distances and number information of valid distance information, a controller receiving a command, a shifter, in response to the shift-enable signal, shifting and outputting reference data in a detection region of a reference frame and outputting the received reference data as it is, a selector, in response to the selection signal, selecting and outputting a part of output data of the shifter or outputting the whole output data, a process element (PE) array receiving current data of a current frame, and a comparator generating operation results for respective block sizes using operation results of the plurality of the PEGs.

Abstract: Provided is a method of decoding a low-density parity-check code (LDPC). The decoding method including an initialization process, a check node update process, a variable node update process, a tentative decoding process, and a parity check process, for a plurality of check nodes and a plurality of variable nodes, further includes detecting at least one inactive variable nodes that do not require variable node update among the variable nodes, the variable node update process is performed only on active variable nodes except for the inactive variable node, and the check node update process is performed without using the inactive variable node.

Abstract: Provided are a motion estimation method and a motion estimation apparatus. The motion estimation apparatus includes a first register storing information on whether to detect first detection positions, a second register storing information on distances and number information of valid distance information, a controller receiving a command, a shifter, in response to the shift-enable signal, shifting and outputting reference data in a detection region of a reference frame and outputting the received reference data as it is, a selector, in response to the selection signal, selecting and outputting a part of output data of the shifter or outputting the whole output data, a process element (PE) array receiving current data of a current frame, and a comparator generating operation results for respective block sizes using operation results of the plurality of the PEGs.

Abstract: The present invention relates to computing circuits and method for running an MPEG-2 AAC or MPEG-4 AAC algorithm efficiently, which is used as an audio compression algorithm in multi-channel high-quality audio systems, on programmable processors. In accordance with the present invention, the IMDCT process which takes large part of the amount of the operations in implementation of an MPEG-2/4 AAC algorithm can be performed in efficient. In addition, while the architecture of the existing digital signal processor is still used, the performance can be improved by means of the addition of the architecture of the address generator, Huffman decoder, and bit processing architecture. After all, to design and change the programmable processor is facilitated.

Abstract: Disclosed is a demapping method of a soft-decision of an efficient soft determining scheme which is applicable to a DVB-2 satellite communication system. The soft-decision demapping method for a digital signal received through a transmission channel in a communication system using a phase shift keying (PSK) scheme includes: selecting reference symbols in an area having a higher probability than a predetermined probability that the received signal will be positioned among all reference symbols on a constellation diagram using a most significant bit (MSB) value of the received signal; and acquiring a maximum value of a log likelihood ratio (LLR) for the selected reference symbols.

Abstract: The present invention relates to computing circuits and method for running an MPEG-2 AAC or MPEG-4 AAC algorithm efficiently, which is used as an audio compression algorithm in multi-channel high-quality audio systems, on programmable processors. In accordance with the present invention, the IMDCT process which takes large part of the amount of the operations in implementation of an MPEG-2/4 AAC algorithm can be performed in efficient. In addition, while the architecture of the existing digital signal processor is still used, the performance can be improved by means of the addition of the architecture of the address generator, Huffman decoder, and bit processing architecture. After all, to design and change the programmable processor is facilitated.

Abstract: The present invention relates to computing circuits and method for running an MPEG-2 AAC or MPEG-4 AAC algorithm efficiently, which is used as an audio compression algorithm in multi-channel high-quality audio systems, on programmable processors. In accordance with the present invention, the IMDCT process which takes large part of the amount of the operations in implementation of an MPEG-2/4 AAC algorithm can be performed in efficient. In addition, while the architecture of the existing digital signal processor is still used, the performance can be improved by means of the addition of the architecture of the address generator, Huffman decoder, and bit processing architecture. After all, to design and change the programmable processor is facilitated.

Abstract: Provided is a frequency error estimating method of a communication system. The method includes receiving a frame, and calculating a frequency error from a SOF field of the received frame.

Abstract: A receiver circuit of a satellite digital video broadcast system includes: a multiplication unit outputting a synchronized reception symbol by multiplying a reception symbol by frequency error information as a feedback; a common autocorrelation unit acquiring autocorrelation values for each symbol by multiplying the synchronized reception symbol by an autocorrelation coefficient; a frame synchronization unit detecting a SOF (Start Of Frame), which is a synchronization word indicating start of a frame, from the autocorrelation values for each symbol; a frequency synchronization unit estimating the frequency error information based on the autocorrelation values for each reception symbol and the SOF; and an SNR estimation unit estimating an SNR (Signal to Noise Ratio) based on the autocorrelation values for each symbol and the SOF.

Abstract: A fast Fourier transform (FFT) operating apparatus and a method thereof carries out an FFT operation in a programmable processor chip. A program controller generates an FFT start signal and controls a programmable processor, and a program memory stores an application of the programmable processor. An FFT address generator removes the looping instruction used for the FFT and a cycle for an address generator, and generates an offset address of a butterfly input data and an operation end signal. An address generator calculates an address of a data memory using the offset address generated in the FFT address generator and a data memory stores data. A data processor carries out an arithmetic and logic operation using the data stored in the data memory and a flag register generates an FFT operation signal.