Abstract: A computing system capable of reducing data movement during an embedding operation and efficiently processing the embedding operation includes a host and a memory system. The host divides a plurality of feature tables, each including a respective plurality of embedding vectors for a respective plurality of elements, into a first feature table group and a second feature table group; generates a first embedding table configured of the first feature table group; and sends a request for a generation operation of a second embedding table configured of the second feature table group to the memory system. The memory system generates the second embedding table according to the generation operation request provided by the host. The host divides the plurality of feature tables into the first feature table group and the second feature table group based on the number of elements included in each of the plurality of feature tables.

Abstract: A computing system capable of reducing data movement during an embedding operation and efficiently processing the embedding operation includes a host and a memory system. The host divides a plurality of feature tables, each including a respective plurality of embedding vectors for a respective plurality of elements, into a first feature table group and a second feature table group; generates a first embedding table configured of the first feature table group; and sends a request for a generation operation of a second embedding table configured of the second feature table group to the memory system. The memory system generates the second embedding table according to the generation operation request provided by the host. The host divides the plurality of feature tables into the first feature table group and the second feature table group based on the number of elements included in each of the plurality of feature tables.

Abstract: A memory system and an operating method thereof are provided. The memory system includes a plurality of memory devices configured to store pieces of partial data obtained by partitioning an embedding table including pieces of vector information about items of a learning model that have already been acquired, and a memory controller configured to obtain, in response to a query received from a host, pieces of data corresponding to the query among the pieces of partial data from each of the plurality of memory devices, perform a pooling operation for generating embedding data using the pieces of data that have been obtained, and provide the embedding data to the host.

Abstract: The present invention relates to an apparatus and method for controlling multi-way NAND flashes using input-output pins. The apparatus for controlling multi-way NAND flashes includes: a NAND flash monitor for confirming each state of a plurality of NAND flashes by using a read status command which checks whether an inner operation of the NAND flash is performed normally; and a scheduler for determining the order in which each of the NAND flashes occupies an input-output bus.