Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a first semiconductor structure including a cell region and a peripheral circuit region, and including a cell capacitor disposed in the cell region and a first insulating layer disposed in the cell region and the peripheral circuit region to cover the cell capacitor; a second semiconductor structure including a cell transistor disposed over the first insulating layer in the cell region and a peripheral circuit transistor disposed over the first insulating layer in the peripheral circuit region; and a first conductor passing through the first insulating layer to electrically connect a first cell source/drain region of the cell transistor and an electrode of the cell capacitor.

Abstract: A sputtering apparatus includes: a first cylindrical target and a second cylindrical target, which are arranged in a first direction and parallel to each other; a first magnet disposed in the first cylindrical target; a second magnet disposed in the second cylindrical target; and a substrate holder spaced apart from the first and second cylindrical targets in a second direction which is perpendicular to the first direction, wherein each of a first angle formed by a first imaginary straight line from a center of the first magnet to a cylindrical axis of the first cylindrical target with a first perpendicular line and a second angle formed by a second imaginary straight line from a center to of the second magnet to a cylindrical axis of the second cylindrical target with a second perpendicular line is in a range of about 30 degrees to about 180 degrees.

Abstract: A semiconductor device includes a first and second channel separation structures extending in a first direction and spaced apart from each other in a second direction, first gate structures spaced apart from each other in the first direction between the first and second channel separation structures and in contact with the first and second channel separation structures, first and second channel patterns including first and second sheet patterns, respectively, spaced apart from each other in a third direction and in contact with the corresponding first and second channel separation structures, first and second source/drain patterns between the first and second channel separation structures, the first source/drain patterns in contact with the first channel patterns and the first channel separation structure, the second source/drain patterns in contact with the second channel patterns and the second channel separation structure, and first gate separation structures between the first and second source/drain patte

Abstract: A semiconductor device includes an active pattern on a substrate extending in a first horizontal direction, a gate electrode on the active pattern extending in a second horizontal direction, a source/drain region on the active pattern, an upper source/drain region apart from the lower source/drain region, a lower source/drain between upper and lower source/drain regions and connected to the lower source/drain region, an upper source/drain connected to an upper source/drain region, an interlayer insulating layer surrounding the upper source/drain region, a through-via on opposing sidewalls in the second horizontal direction extending through the interlayer insulating layer in the vertical direction, the through-via being spaced from the upper source/drain region and upper source/drain contact in the second horizontal direction, the through-via being connected to the lower source/drain contact, and a dam structure on each of the opposing sidewalls in the horizontal direction of the upper source/drain region.

Abstract: A semiconductor device includes a substrate, a first active pattern disposed on the substrate, a second active pattern stacked on the first active pattern, a first gate structure extending to intersect the first active pattern and the second active pattern, a second gate structure spaced apart from the first gate structure and extending to intersect the first active pattern and the second active pattern, a first epitaxial pattern interposed between the first gate structure and the second gate structure, and connected to the first active pattern, a second epitaxial pattern interposed between the first gate structure and the second gate structure, and connected to the second active pattern, an insulating pattern interposed between the first epitaxial pattern and the second epitaxial pattern, and a semiconductor film interposed between the insulating pattern and the second epitaxial pattern, the semiconductor film extending along a top surface of the insulating pattern.

Abstract: A semiconductor device includes a substrate, a first sheet pattern on the substrate, a gate electrode on the substrate and surrounding the first sheet pattern, a first source/drain pattern and a second source/drain pattern respectively connected to a first end and a second end of the first sheet pattern, a contact blocking pattern on a lower side of the second source/drain pattern, a first source/drain contact extending in a first direction and connected to the first source/drain pattern, and a second source/drain contact connected to the second source/drain pattern and extending in the first direction to contact an upper surface of the contact blocking pattern. A depth from an upper surface of the gate electrode to a lowermost portion of the first source/drain contact may be greater than a depth from the upper surface of the gate electrode to the upper surface of the contact blocking pattern.

Abstract: A semiconductor device includes a substrate, an active pattern on the substrate, a plurality of lower nanosheets stacked on the active pattern, a separation structure spaced apart from the plurality of lower nanosheets in the vertical direction and disposed on the plurality of lower nanosheets, and including first to third layers sequentially stacked on each other, a plurality of upper nanosheets spaced apart from the separation structure in the vertical direction and disposed on the separation structure, and stacked on the separation structure, and a gate electrode extending in a second horizontal direction different from the first horizontal direction, and surrounding the separation structure, each of the plurality of lower nanosheets, and each of the plurality of upper nanosheets. The first and third layers include the same material, and each of the first layer and the third layer includes a material different from a material of the second layer.

Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.

Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.

Abstract: An integrated circuit (IC) device includes a first and a second fin-type active region protruding from a first region and a second region, respectively, of a substrate, a first and a second gate line, and a first and a second source/drain region. The first fin-type active region has a first top surface and a first recess has a first depth from the first top surface. The first source/drain region fills the first recess and has a first width. The second fin-type active region has a second top surface and a second recess has a second depth from the second top surface. The second depth is greater than the first depth. The second source/drain region fills the second recess and has a second width. The second width is greater than the first width.

Abstract: An integrated circuit (IC) device includes a first and a second fin-type active region protruding from a first region and a second region, respectively, of a substrate, a first and a second gate line, and a first and a second source/drain region. The first fin-type active region has a first top surface and a first recess has a first depth from the first top surface. The first source/drain region fills the first recess and has a first width. The second fin-type active region has a second top surface and a second recess has a second depth from the second top surface. The second depth is greater than the first depth. The second source/drain region fills the second recess and has a second width. The second width is greater than the first width.

Abstract: A semiconductor device including a first fin protruding on a substrate and extending in a first direction; a first gate electrode on the first fin, the first gate electrode intersecting the first fin; a first trench formed within the first fin at a side of the first gate electrode; a first epitaxial layer filling a portion of the first trench, wherein a thickness of the first epitaxial layer becomes thinner closer to a sidewall of the first trench; and a second epitaxial layer filling the first trench on the first epitaxial layer, wherein a boron concentration of the second epitaxial layer is greater than a boron concentration of the first epitaxial layer.

Abstract: An integrated circuit (IC) device includes a first and a second fin-type active region protruding from a first region and a second region, respectively, of a substrate, a first and a second gate line, and a first and a second source/drain region. The first fin-type active region has a first top surface and a first recess has a first depth from the first top surface. The first source/drain region fills the first recess and has a first width. The second fin-type active region has a second top surface and a second recess has a second depth from the second top surface. The second depth is greater than the first depth. The second source/drain region fills the second recess and has a second width. The second width is greater than the first width.

Abstract: An integrated circuit (IC) device includes a first and a second fin-type active region protruding from a first region and a second region, respectively, of a substrate, a first and a second gate line, and a first and a second source/drain region. The first fin-type active region has a first top surface and a first recess has a first depth from the first top surface. The first source/drain region fills the first recess and has a first width. The second fin-type active region has a second top surface and a second recess has a second depth from the second top surface. The second depth is greater than the first depth. The second source/drain region fills the second recess and has a second width. The second width is greater than the first width.

Abstract: An integrated circuit (IC) device includes a first and a second fin-type active region protruding from a first region and a second region, respectively, of a substrate, a first and a second gate line, and a first and a second source/drain region. The first fin-type active region has a first top surface and a first recess has a first depth from the first top surface. The first source/drain region fills the first recess and has a first width. The second fin-type active region has a second top surface and a second recess has a second depth from the second top surface. The second depth is greater than the first depth. The second source/drain region fills the second recess and has a second width. The second width is greater than the first width.

Abstract: A semiconductor device including a first fin protruding on a substrate and extending in a first direction; a first gate electrode on the first fin, the first gate electrode intersecting the first fin; a first trench formed within the first fin at a side of the first gate electrode; a first epitaxial layer filling a portion of the first trench, wherein a thickness of the first epitaxial layer becomes thinner closer to a sidewall of the first trench; and a second epitaxial layer filling the first trench on the first epitaxial layer, wherein a boron concentration of the second epitaxial layer is greater than a boron concentration of the first epitaxial layer.

Abstract: A semiconductor device including a first fin protruding on a substrate and extending in a first direction; a first gate electrode on the first fin, the first gate electrode intersecting the first fin; a first trench formed within the first fin at a side of the first gate electrode; a first epitaxial layer filling a portion of the first trench, wherein a thickness of the first epitaxial layer becomes thinner closer to a sidewall of the first trench; and a second epitaxial layer filling the first trench on the first epitaxial layer, wherein a boron concentration of the second epitaxial layer is greater than a boron concentration of the first epitaxial layer.

Abstract: An integrated circuit (IC) device includes a first and a second fin-type active region protruding from a first region and a second region, respectively, of a substrate, a first and a second gate line, and a first and a second source/drain region. The first fin-type active region has a first top surface and a first recess has a first depth from the first top surface. The first source/drain region fills the first recess and has a first width. The second fin-type active region has a second top surface and a second recess has a second depth from the second top surface. The second depth is greater than the first depth. The second source/drain region fills the second recess and has a second width. The second width is greater than the first width.

Abstract: A semiconductor device including a first fin protruding on a substrate and extending in a first direction; a first gate electrode on the first fin, the first gate electrode intersecting the first fin; a first trench formed within the first fin at a side of the first gate electrode; a first epitaxial layer filling a portion of the first trench, wherein a thickness of the first epitaxial layer becomes thinner closer to a sidewall of the first trench; and a second epitaxial layer filling the first trench on the first epitaxial layer, wherein a boron concentration of the second epitaxial layer is greater than a boron concentration of the first epitaxial layer.

Abstract: A semiconductor device includes a substrate having a first region and a second region, a plurality of first gate structures in the first region, the first gate structures being spaced apart from each other by a first distance, a plurality of second gate structures in the second region, the second gate structures being spaced apart from each other by a second distance, a first spacer on sidewalls of the first gate structures, a dielectric layer on the first spacer, a second spacer on sidewalls of the second gate structures, and a third spacer on the second spacer.