Abstract: An organic light emitting diode display device and a method for manufacturing the same are disclosed. The organic light emitting diode display device includes: a substrate having first and second subpixels, each of the first and second subpixels having an emission area; a thin film transistor in each of the first and second subpixels; a first anode connected to the thin film transistor and having a first area; and a second anode having a second area greater than the first area, wherein the second anode is disposed on the first anode to cover the first anode.

Abstract: A display apparatus can include at least one light-emitting device on a device substrate, an encapsulating element on the device substrate and covering the light-emitting device, an encapsulation substrate on the encapsulating element and including a metal, and a surface particle layer surrounding at least a portion of the encapsulation substrate. The surface particle layer can include metal particles dispersed at a surface of the encapsulation substrate. The surface particle layer can have a thermal conductivity that is higher than a thermal conductivity of the encapsulation substrate.

Abstract: A method includes receiving data for a desired output frequency of an output clock of a phase locked loop (PLL) circuit. The method includes determining a preset value for a digitally controlled oscillator (DCO) of the PLL circuit, determining first gain coefficients and second gain coefficients for a filter of the PLL circuit, and determining ratio values for a divider circuit of the PLL circuit based on the data. The method includes providing the preset value to the DCO, the first gain coefficients to the filter, and the ratio values to the divider circuit while the PLL circuit operates in an open-loop configuration. The method includes subsequently operating the PLL circuit in a closed-loop configuration by connecting the filter to the DCO, and providing the second gain coefficients to the filter in response to detecting a phase lock of the PLL circuit operating in the closed-loop configuration.

Abstract: A phase lock loop circuit includes a phase frequency detector, a voltage controlled oscillator, a phase interpolator, a clock signal selector, a selection module, a multiplexer, and a divider. The phase frequency detector compares phases of a reference clock and frequency divided output signals and generates an error signal. The voltage controlled oscillator, based on the error signal, generates a phase lock loop output signal and output clock signals. The phase interpolator phase interpolates the output clock signals to generate an interpolator output signal. The clock signal selector selects one of the output clock signals. The selection module generates a selection signal based on states of the interpolator output and selected output clock signals. The multiplexer, based on the selection signal, selects the interpolator output signal or the selected output clock signal. The divider frequency divides an output of the multiplexer to provide the frequency divided output signal.

Abstract: A digital locking loop circuit (DLLC), such as a digital phase-locked loop or digital delay-locked loop, includes a digitally-controlled frequency generator, a digital loop filter configured to output a digital control signal for the frequency generator, and a multi-stage time-to-digital converter to detect phase error between an input reference clock signal and an output signal fed back from the frequency generator, to adjust the digitally-controlled frequency generator to decrease the phase error. Each phase-error detection stage detects a phase error component at a respective resolution, and combinatorial logic combines the components into a phase error signal. The plurality of stages may operate in parallel to provide different portions of the phase error signal. The DLLC may include a fractional phase interpolator to adjust the target frequency by a fractional amount, and one of the stages includes conversion circuitry to compensate for a fractional phase. A method also is provided.

Abstract: In some implementations, a system includes a phase locked loop (PLL) circuit and a digital control unit. The PLL circuit includes a digital loop filter, a digitally controlled oscillator (DCO), and a divider circuit. The digital control unit is configured determine a preset value for the DCO; determine initial gain coefficients and final gain coefficients for the digital loop filter; determine N/R values for the divider circuit; while the PLL circuit is operating in an open-loop configuration, provide the preset value to the DCO, the initial gain coefficients to the digital loop filter, and the N/R values to the divider circuit; after providing the preset value, initial gain coefficients, and N/R values, initiate operation of the PLL circuit in the closed-loop configuration; and in response to detection of a phase lock of the PLL circuit operating in the closed-loop configuration, provide the final gain coefficients to the digital loop filter.

Abstract: The present disclosure describes variable gain amplifiers with gain-based compensation. In some embodiments, a variable gain amplifier (VGA) includes a gain stage, an output stage, a compensation stage, and a capacitor coupled between respective outputs of the gain stage and compensation stage. A gain of the VGA is configured, based on a gain setting, to amplify signals received by the variable gain amplifier. A gain of the compensation stage is configured, based on the gain setting, to alter an effective capacitance of the capacitor, which is applied to the output of the gain stage for compensation of the VGA. By altering the effective capacitance based on the gain setting of the VGA, compensation capacitance is adjusted continuously with changes in the gain setting and at a similar resolution. In various embodiments, the continuous adjustment of the compensation capacitance across different gain levels prevents discontinuities in amplifier compensation.

Abstract: A digital locking loop circuit (DLLC), such as a digital phase-locked loop or digital delay-locked loop, includes a digitally-controlled frequency generator, a digital loop filter configured to output a digital control signal for the frequency generator, and a multi-stage time-to-digital converter to detect phase error between an input reference clock signal and an output signal fed back from the frequency generator, to adjust the digitally-controlled frequency generator to decrease the phase error. Each phase-error detection stage detects a phase error component at a respective resolution, and combinatorial logic combines the components into a phase error signal. The plurality of stages may operate in parallel to provide different portions of the phase error signal. The DLLC may include a fractional phase interpolator to adjust the target frequency by a fractional amount, and one of the stages includes conversion circuitry to compensate for a fractional phase. A method also is provided.

Abstract: A common mode filter includes: an insulator; a coil pattern embedded within in the insulator; and a magnetic layer including a layer of material filled with different-size magnetic particles, wherein a surface of the magnetic layer is adhered to the insulator.

Abstract: A precompensation circuit can include: a rising edge interpolator circuit configured to generate a phase shifted rising edge data signal; a falling edge interpolator circuit configured to generate a phase shifted falling edge data signal; a multiplexer circuit coupled with the rising edge interpolator circuit and with the falling edge interpolator circuit to multiplex the phase shifted rising edge data signal and the phase shifted falling edge data signal into an output data signal responsive to a select signal; and a control circuit coupled with the select input of the multiplexer circuit to control production of the output data signal, wherein the control circuit is further coupled with both the rising edge interpolator circuit and the falling edge interpolator circuit to change the select signal to the multiplexer circuit at times determined by both the phase shifted rising edge data signal and the phase shifted falling edge data signal.

Abstract: A common mode filter includes: an insulator; a coil pattern embedded within in the insulator; and a magnetic layer including a layer of material filled with different-size magnetic particles, wherein a surface of the magnetic layer is adhered to the insulator.

Abstract: A coil component and a method of manufacturing a coil component are disclosed. The coil component includes an insulation layer including a coil conductor, and a magnetic-resin composite layer disposed on the insulation layer. The magnetic-resin composite layer includes a magnetic core.

Abstract: A method of manufacturing an organic light emitting display panel forming a protective insulating film in a luminescent region without causing defects in a pattern is disclosed. The method of manufacturing an organic light emitting display panel includes forming a substrate having a luminescent region and a pad region, simultaneously forming a light emitting cell in the luminescent region and an organic pattern in the pad region, forming a protective insulating film over the substrate, bonding the substrate provided with the protective insulating film and the sealing substrate using an adhesive film formed in a region corresponding to the luminescent region, cutting the bonded substrate provided with the protective insulating film and the sealing substrate into a plurality of unit panels to expose the pad region, and removing the protective insulating film and the organic pattern in the exposed pad region.

Abstract: A circuit including an amplifier, a transistor, and first, second and third resistances. The amplifier includes an input and an output. The amplifier receives an input signal. A cycle of the input signal includes first and second pulses. The input signal is asymmetrical such that the first pulse has a different peak magnitude than the second pulse. The transistor is connected to the input and the output. The first, second, and third resistances are each connected to the input of the amplifier. The second resistance receives a first input voltage. The third resistance receives a second input voltage. The input signal is based on the first resistance and the first and second input voltages. The amplifier corrects some asymmetry of the input signal to provide an output signal. An amount of asymmetry of the output signal is based on (i) the input signal, and (ii) a state of the transistor.

Abstract: Embodiments of the invention provide a copper clad laminate, and more particularly, to a copper clad laminate and a method for manufacturing the same capable of increasing a peel strength by adding a stress relaxation filler to an insulating layer of a copper clad laminate, along with an inorganic filler. To improve an adhesion of a substrate, the stress relaxation filler is distributed into the resin, along with the inorganic filler, and is entirely distributed into the varnish, and is more effectively added to the vicinity of a bonded interface between the insulating layer and the copper clad layer, thereby improving the overall adhesion.

Abstract: A circuit including an amplifier, a transistor, and first, second and third resistances. The amplifier includes an input and an output. The amplifier receives an input signal. A cycle of the input signal includes first and second pulses. The input signal is asymmetrical such that the first pulse has a different peak magnitude than the second pulse. The transistor is connected to the input and the output. The first, second, and third resistances are each connected to the input of the amplifier. The second resistance receives a first input voltage. The third resistance receives a second input voltage. The input signal is based on the first resistance and the first and second input voltages. The amplifier corrects some asymmetry of the input signal to provide an output signal. An amount of asymmetry of the output signal is based on (i) the input signal, and (ii) a state of the transistor.

Abstract: In one embodiment, an apparatus an amplifier configured to receive an asymmetric signal. A first resistance is coupled between an input node and an output node of the amplifier, the input node receiving the asymmetric signal. A second resistance is coupled to the input node of the amplifier. The second resistance includes a linear resistor. A third resistance is coupled to the second resistance. The third resistance is varied to adjust an amount of asymmetric correction provided by the amplifier to correct the asymmetric signal at the output node. The amount of asymmetric correction is a function of the first resistance and a combination of the second resistance and the third resistance.

Abstract: A method of manufacturing an organic light emitting display panel forming a protective insulating film in a luminescent region without causing defects in a pattern is disclosed. The method of manufacturing an organic light emitting display panel includes forming a substrate having a luminescent region and a pad region, simultaneously forming a light emitting cell in the luminescent region and an organic pattern in the pad region, forming a protective insulating film over the substrate, bonding the substrate provided with the protective insulating film and the sealing substrate using an adhesive film formed in a region corresponding to the luminescent region, cutting the bonded substrate provided with the protective insulating film and the sealing substrate into a plurality of unit panels to expose the pad region, and removing the protective insulating film and the organic pattern in the exposed pad region.

Abstract: In one embodiment, an apparatus an amplifier configured to receive an asymmetric signal. A first resistance is coupled between an input node and an output node of the amplifier, the input node receiving the asymmetric signal. A second resistance is coupled to the input node of the amplifier. The second resistance includes a linear resistor. A third resistance is coupled to the second resistance. The third resistance is varied to adjust an amount of asymmetric correction provided by the amplifier to correct the asymmetric signal at the output node. The amount of asymmetric correction is a function of the first resistance and a combination of the second resistance and the third resistance.