Patents by Inventor Myung-Jin Kang
Myung-Jin Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145167Abstract: A multilayer capacitor includes a body including dielectric layers and internal electrodes and external electrodes disposed on an external surface of the body and connected to the internal electrodes. The body includes a first surface and a second surface to which the internal electrodes are exposed, the first surface and the second surface opposing each other in a first direction, a third surface and a fourth surface opposing each other in a second direction which is a direction in which the dielectric layers are stacked, and a fifth surface and a sixth surface opposing each other in a third direction. At least one of the internal electrodes include a first bottleneck structure having a first directional length of a third-directional outer region smaller than an inner region thereof and a second bottleneck structure having a third directional length of a first directional outer region smaller than an inner region thereof.Type: ApplicationFiled: January 10, 2024Publication date: May 2, 2024Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jong Ho Lee, Myung Chan Son, Sim Chung Kang, Eun Jin Shim, Sun Hwa Kim, Byung Soo Kim
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Patent number: 11944661Abstract: The present invention provides a pharmaceutical composition for prevention or treatment of a stress disease and depression, the pharmaceutical composition be safely useable without toxicity and side effects by using an extract of leaves of Vaccinium bracteatum Thunb., which is natural resource of Korea, so that the reduction of manufacturing and production costs and the import substitution and export effects can be expected through the replacement of a raw material for preparation with a plant inhabiting in nature.Type: GrantFiled: February 7, 2018Date of Patent: April 2, 2024Assignee: JEONNAM BIOINDUSTRY FOUNDATIONInventors: Chul Yung Choi, Dool Ri Oh, Yu Jin Kim, Eun Jin Choi, Hyun Mi Lee, Dong Hyuck Bae, Kyo Nyeo Oh, Myung-A Jung, Ji Ae Hong, Kwang Su Kim, Hu Won Kang, Jae Yong Kim, Sang O Pan, Sung Yoon Park, Rack Seon Seong
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Patent number: 11923362Abstract: An integrated circuit (IC) device includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a first nanosheet disposed above an upper surface of the fin-type active area with a first separation space therebetween; a second nanosheet disposed above the first nanosheet with a second separation space therebetween; a gate line extending on the substrate in a second horizontal direction intersecting the first horizontal direction, at least a portion of the gate line being disposed in the second separation space; and a bottom insulation structure disposed in the first separation space.Type: GrantFiled: May 9, 2023Date of Patent: March 5, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Myung-gil Kang, Beom-jin Park, Geum-jong Bae, Dong-won Kim, Jung-gil Yang
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Patent number: 10439033Abstract: A semiconductor device can include a substrate with a first source/drain and a second source/drain in the substrate. A first ohmic contact pattern can be in an uppermost surface of the first source/drain, where the first ohmic contact pattern includes a first semiconductor alloyed with a first metal. A second ohmic contact pattern can be in an uppermost surface of the second source/drain, where the second ohmic contact pattern includes a second semiconductor that is different than the first semiconductor and is alloyed with a second metal that is different than the first metal.Type: GrantFiled: November 14, 2016Date of Patent: October 8, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Junjie Xiong, Dongho Cha, Myung Jin Kang, Kihoon Do
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Publication number: 20170062579Abstract: A semiconductor device can include a substrate with a first source/drain and a second source/drain in the substrate. A first ohmic contact pattern can be in an uppermost surface of the first source/drain, where the first ohmic contact pattern includes a first semiconductor alloyed with a first metal. A second ohmic contact pattern can be in an uppermost surface of the second source/drain, where the second ohmic contact pattern includes a second semiconductor that is different than the first semiconductor and is alloyed with a second metal that is different than the first metal.Type: ApplicationFiled: November 14, 2016Publication date: March 2, 2017Inventors: Junjie Xiong, Dongho Cha, Myung Jin Kang, Kihoon Do
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Patent number: 9515150Abstract: Provided are semiconductor devices and methods of manufacturing the same. The methods include providing a substrate including a first region and a second region, forming first mask patterns in the first region, and forming second mask patterns having an etch selectivity with respect to the first mask patterns in the second region. The first mask patterns and the second mask patterns are formed at the same time.Type: GrantFiled: June 19, 2014Date of Patent: December 6, 2016Assignee: Samsung Electronics Co, Ltd.Inventors: Junjie Xiong, Dongho Cha, Myung Jin Kang, Kihoon Do
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Patent number: 9034719Abstract: A method of forming a variable resistive memory device includes forming a conductive pattern that alternates with a first insulation pattern along a first direction on a substrate that is parallel with a surface of the substrate, forming a preliminary sacrificial pattern on the conductive pattern that contacts a sidewall of the first insulation pattern, etching the conductive pattern using the preliminary sacrificial pattern as an etch masks to form a preliminary bottom electrode pattern, patterning the preliminary sacrificial pattern and the preliminary bottom electrode pattern to form a sacrificial pattern and a bottom electrode pattern that each include at least two portions which are separated from each other along a second direction intersecting the first direction, and replacing the sacrificial pattern with a variable resistive pattern.Type: GrantFiled: June 26, 2014Date of Patent: May 19, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Myung Jin Kang
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Publication number: 20150028399Abstract: Provided are semiconductor devices and methods of manufacturing the same. The methods include providing a substrate including a first region and a second region, forming first mask patterns in the first region, and forming second mask patterns having an etch selectivity with respect to the first mask patterns in the second region. The first mask patterns and the second mask patterns are formed at the same time.Type: ApplicationFiled: June 19, 2014Publication date: January 29, 2015Inventors: Junjie Xiong, Dongho Cha, Myung Jin Kang, Kihoon Do
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Publication number: 20140308797Abstract: A method of forming a variable resistive memory device includes forming a conductive pattern that alternates with a first insulation pattern along a first direction on a substrate that is parallel with a surface of the substrate, forming a preliminary sacrificial pattern on the conductive pattern that contacts a sidewall of the first insulation pattern, etching the conductive pattern using the preliminary sacrificial pattern as an etch masks to form a preliminary bottom electrode pattern, patterning the preliminary sacrificial pattern and the preliminary bottom electrode pattern to form a sacrificial pattern and a bottom electrode pattern that each include at least two portions which are separated from each other along a second direction intersecting the first direction, and replacing the sacrificial pattern with a variable resistive pattern.Type: ApplicationFiled: June 26, 2014Publication date: October 16, 2014Inventor: Myung Jin KANG
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Patent number: 8824187Abstract: A phase change memory device includes a plurality of word lines, a plurality of lower electrodes, and a plurality of phase change material patterns. The plurality of word lines extend in a first direction and the plurality of word lines are arranged along a second direction perpendicular to the first direction. The lower electrodes are on the word lines and the lower electrodes are arranged in a direction diagonal to the first direction by a first angle. Each of the plurality of phase change material patterns are on a corresponding one of the plurality of lower electrodes.Type: GrantFiled: June 4, 2012Date of Patent: September 2, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Jin Park, Ki-Hoon Do, Myung-Jin Kang
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Patent number: 8765564Abstract: A method of forming a variable resistive memory device includes forming a conductive pattern that alternates with a first insulation pattern along a first direction on a substrate that is parallel with a surface of the substrate, forming a preliminary sacrificial pattern on the conductive pattern that contacts a sidewall of the first insulation pattern, etching the conductive pattern using the preliminary sacrificial pattern as an etch masks to form a preliminary bottom electrode pattern, patterning the preliminary sacrificial pattern and the preliminary bottom electrode pattern to form a sacrificial pattern and a bottom electrode pattern that each include at least two portions which are separated from each other along a second direction intersecting the first direction, and replacing the sacrificial pattern with a variable resistive pattern.Type: GrantFiled: June 13, 2012Date of Patent: July 1, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Myung Jin Kang
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Patent number: 8765521Abstract: According to example embodiments, a variable resistance memory device include an ohmic pattern on a substrate; a first electrode pattern including a first portion that has a plate shape and contacts a top surface of the ohmic pattern and a second portion that extends from one end of the first portion to a top; a variable resistance pattern electrically connected to the first electrode pattern; and a second electrode pattern electrically connected to the variable resistance pattern, wherein one end of the ohmic pattern and the other end of the first portion are disposed on the same plane.Type: GrantFiled: December 30, 2013Date of Patent: July 1, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Myung Jin Kang, Youngnam Hwang
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Publication number: 20140113429Abstract: According to example embodiments, a variable resistance memory device include an ohmic pattern on a substrate; a first electrode pattern including a first portion that has a plate shape and contacts a top surface of the ohmic pattern and a second portion that extends from one end of the first portion to a top; a variable resistance pattern electrically connected to the first electrode pattern; and a second electrode pattern electrically connected to the variable resistance pattern, wherein one end of the ohmic pattern and the other end of the first portion are disposed on the same plane.Type: ApplicationFiled: December 30, 2013Publication date: April 24, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Myung Jin KANG, Youngnam HWANG
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Patent number: 8653493Abstract: According to example embodiments, a variable resistance memory device include an ohmic pattern on a substrate; a first electrode pattern including a first portion that has a plate shape and contacts a top surface of the ohmic pattern and a second portion that extends from one end of the first portion to a top; a variable resistance pattern electrically connected to the first electrode pattern; and a second electrode pattern electrically connected to the variable resistance pattern, wherein one end of the ohmic pattern and the other end of the first portion are disposed on the same plane.Type: GrantFiled: February 9, 2012Date of Patent: February 18, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Myung Jin Kang, Youngnam Hwang
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Patent number: 8598010Abstract: Methods of forming a variable-resistance memory device include patterning an interlayer dielectric layer to define an opening therein that exposes a bottom electrode of a variable-resistance memory cell, on a memory cell region of a substrate (e.g., semiconductor substrate). These methods further include depositing a layer of variable-resistance material (e.g., phase-changeable material) onto the exposed bottom electrode in the opening and onto a first portion of the interlayer dielectric layer extending opposite a peripheral circuit region of the substrate. The layer of variable-resistance material and the first portion of the interlayer dielectric layer are then selectively etched in sequence to define a recess in the interlayer dielectric layer. The layer of variable-resistance material and the interlayer dielectric layer are then planarized to define a variable-resistance pattern within the opening.Type: GrantFiled: April 20, 2011Date of Patent: December 3, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Heung Jin Joo, JaeHee Oh, Byoungjae Bae, Myung Jin Kang
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Publication number: 20130105757Abstract: A phase change memory device includes a plurality of word lines, a plurality of lower electrodes, and a plurality of phase change material patterns. The plurality of word lines extend in a first direction and the plurality of word lines are arranged along a second direction perpendicular to the first direction. The lower electrodes are on the word lines and the lower electrodes are arranged in a direction diagonal to the first direction by a first angle. Each of the plurality of phase change material patterns are on a corresponding one of the plurality of lower electrodes.Type: ApplicationFiled: June 4, 2012Publication date: May 2, 2013Inventors: Tae-Jin PARK, Ki-Hoon DO, Myung-Jin KANG
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Publication number: 20120315737Abstract: A method of forming a variable resistive memory device includes forming a conductive pattern that alternates with a first insulation pattern along a first direction on a substrate that is parallel with a surface of the substrate, forming a preliminary sacrificial pattern on the conductive pattern that contacts a sidewall of the first insulation pattern, etching the conductive pattern using the preliminary sacrificial pattern as an etch masks to form a preliminary bottom electrode pattern, patterning the preliminary sacrificial pattern and the preliminary bottom electrode pattern to form a sacrificial pattern and a bottom electrode pattern that each include at least two portions which are separated from each other along a second direction intersecting the first direction, and replacing the sacrificial pattern with a variable resistive pattern.Type: ApplicationFiled: June 13, 2012Publication date: December 13, 2012Inventor: Myung Jin KANG
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Publication number: 20120211720Abstract: According to example embodiments, a variable resistance memory device include an ohmic pattern on a substrate; a first electrode pattern including a first portion that has a plate shape and contacts a top surface of the ohmic pattern and a second portion that extends from one end of the first portion to a top; a variable resistance pattern electrically connected to the first electrode pattern; and a second electrode pattern electrically connected to the variable resistance pattern, wherein one end of the ohmic pattern and the other end of the first portion are disposed on the same plane.Type: ApplicationFiled: February 9, 2012Publication date: August 23, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Myung Jin Kang, Youngnam Hwang
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Patent number: 8237141Abstract: A non-volatile memory device including a phase-change material, which has a low operating voltage and low power consumption, includes a lower electrode; a phase-change material layer formed on the lower electrode so as to be electrically connected to the lower electrode, wherein the phase-change material layer includes a phase-change material having a composition represented by InXSbYTeZ or, alternatively, with substitutions of silicon and/or tin for indium, arsenic and/or bismuth for antimony, and selenium for tellurium; and an upper electrode formed on the phase-change material layer so as to be electrically connected to the phase-change material layer.Type: GrantFiled: January 19, 2010Date of Patent: August 7, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Myung-jin Kang, Jun-soo Bae, Doo-hwan Park, Eun-hee Cho
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Patent number: 8133757Abstract: A phase changeable memory unit includes a lower electrode, an insulating interlayer structure having an opening, a phase changeable material layer and an upper electrode. The lower electrode is formed on a substrate. The insulating interlayer structure has an opening and is formed on the lower electrode and the substrate. The opening exposes the lower electrode and has a width gradually decreasing downward. The phase changeable material layer fills the opening and partially covers an upper face of the insulating interlayer structure. The upper electrode is formed on the phase changeable material layer.Type: GrantFiled: December 3, 2009Date of Patent: March 13, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Suk Kwon, Young-Soo Lim, Sung-Un Kwon, Yong-Ho Ha, Jeong-Hee Park, Joon-Sang Park, Myung-Jin Kang, Doo-Hwan Park