Abstract: Disclosure provides a two-segment electromagnet stirring member, and a two-segment electromagnet semi-solid die-casting apparatus including the same, and a die-casting method using the same. The two-segment electromagnet stirring member includes a plurality of magnetic field generation parts therein, and includes a first electromagnetic stirring part and a second electromagnetic stirring part separated from each other. The first electromagnetic stirring part and the second electromagnetic stirring part are coupled to each other in a ring shape to surround an outer circumferential surface of a sleeve to perform electromagnetic stirring to molten metal in the sleeve, and are coupled to each other so as to position the plurality of magnetic field generation parts at radially equal gaps around the sleeve.

Abstract: The present specification provides a method for preparing a styrene monomer including preparing a styrene monomer of Chemical Formula 2 by reacting a compound represented by Chemical Formula 1 in the presence of phosphoric acid, wherein the phosphoric acid is used in 100 mol % or greater based on 100 mol % of the compound represented by Chemical Formula 1.

Abstract: The present specification provides a method for preparing a styrene monomer including preparing a styrene monomer of Chemical Formula 2 by reacting a compound represented by Chemical Formula 1 in the presence of phosphoric acid, wherein the phosphoric acid is used in 100 mol % or greater based on 100 mol % of the compound represented by Chemical Formula 1.

Abstract: The diffusion structures in CMOS devices can be changed to minimize the effects of IR drop on those devices. A simulation can be run before tape-off to determine which transistors are at risk. The area of the source region and/or the width of the drain region of the at-risk transistor(s) can be adjusted to change the capacitive and/or resistive capability of the transistor(s). These altered diffusion structures can reduce the peak IR drop value, such as by an amount in the range of 8%-30% of the original peak noise, to prevent the chip from malfunctioning due to the resultant noise. The reduction in IR drop can be balanced with the timing delays introduced by the increased capacitance of the source area. An optimal combination of source area and drain width can be obtained and instituted during the simulation and testing processes.

Abstract: The diffusion structures in CMOS devices can be changed to minimize the effects of IR drop on those devices. A simulation can be run before tape-off to determine which transistors are at risk. The area of the source region and/or the width of the drain region of the at-risk transistor(s) can be adjusted to change the capacitive and/or resistive capability of the transistor(s). These altered diffusion structures can reduce the peak IR drop value, such as by an amount in the range of 8%–30% of the original peak noise, to prevent the chip from malfunctioning due to the resultant noise. The reduction in IR drop can be balanced with the timing delays introduced by the increased capacitance of the source area. An optimal combination of source area and drain width can be obtained and instituted during the simulation and testing processes.